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MC74HC533A

Motorola
Part Number MC74HC533A
Manufacturer Motorola
Description Octal 3-State Inverting Transparent Latch
Published Aug 31, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Inverting Transparent Latch High–Performance Silicon–Gate CMOS The...
Datasheet PDF File MC74HC533A PDF File

MC74HC533A
MC74HC533A

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Inverting Transparent Latch High–Performance Silicon–Gate CMOS The MC54/74HC533A is identical in pinout to the LS533.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.
e.
, the outputs change asynchronously) when Latch Enable is high.
The Data appears at the outputs in inverted form.
When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state.
Thus, data may be latched even when the outputs are not enabled.
The HC533A is identical in function to the HC563 but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.
This device is similar in function to the HC373A, which has noninverting outputs.
• • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.
0 to 6.
0 V Low Input Current: 1.
0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No.
7A • Chip Complexity: 256 FETs or 64 Equivalent Gates MC54/74HC533A J SUFFIX CERAMIC PACKAGE CASE 732–03 1 20 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW Ceramic Plastic SOIC PIN ASSIGNMENT OUTPUT ENABLE Q0 D0 D1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LATCH ENABLE LOGIC DIAGRAM 2 5 6 9 12 15 16 19 Q1 Q2 D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 INVERTING OUTPUTS D2 D3 Q3 GND FUNCTION TABLE Inputs Output Enable L L L H Latch Enable H H L X D H L X X Output Q L H No Change Z LATCH ENABLE 11 1 OUTPUT ENABLE PIN 20 = VCC PIN ...


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