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MSM514221B

OKI electronic componets
Part Number MSM514221B
Manufacturer OKI electronic componets
Description DRAM / FAST PAGE MODE TYPE
Published Sep 4, 2005
Detailed Description E2L0029-17-Y1 ¡ Semiconductor MSM514221B ¡ Semiconductor 262,263-Word ¥ 4-Bit Field Memory This version: Jan. 1998 MSM...
Datasheet PDF File MSM514221B PDF File

MSM514221B
MSM514221B

Overview
E2L0029-17-Y1 ¡ Semiconductor MSM514221B ¡ Semiconductor 262,263-Word ¥ 4-Bit Field Memory This version: Jan.
1998 MSM514221B Previous version: Dec.
1996 DESCRIRTION The OKI MSM514221B is a high performance 1-Mbit, 256K ¥ 4-bit, Field Memory.
It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems.
It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively.
The MSM514221B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others.
The 1-Mbit capacity fits one field of a conventional NTSC TV screen.
Each of the 4-bit planes has separate serial write and read ports.
These employ independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported that allow alternate data rates between write and read data streams.
The MSM514221B provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is on.
Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.
The MSM514221B's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing.
The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 ¥ 4-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings.
The MSM514...


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