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MT8LSDT3264A

Part Number	MT8LSDT3264A
Manufacturer	Micron Technology
Description	SYNCHRONOUS DRAM MODULE
Published	Sep 16, 2005
Detailed Description	256MB / 512MB (x64) 168-PIN SDRAM DIMMs SYNCHRONOUS DRAM MODULE Features • PC100- and PC133-compliant • JEDEC-standard ...
Datasheet	MT8LSDT3264A PDF File

Overview

256MB / 512MB (x64) 168-PIN SDRAM DIMMs SYNCHRONOUS DRAM MODULE Features • PC100- and PC133-compliant • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • Unbuffered • 256MB (32 Meg x 64), 512MB (64 Meg x 64) • Single +3.
3V ±0.
3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes • 64ms, 8,192 cycle Auto Refresh cycle • Self Refresh Mode • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) MT8LSDT3264A(I) - 256MB MT16LSDT6464A(I) - 512MB For the latest data sheet, please refer to the Micron Web site: www.
micron.
com/moduleds Figure 1: 168-Pin DIMM (MO–161) Standard Low Profile OPTIONS • Package Unbuffered 168-pin DIMM (gold) • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C)1 • Memory Clock/CAS Latency (133 MHz)/CL = 2 (133 MHz)/CL = 3 (100 MHz)/CL = 2 NOTE: MARKING A G None I -13E -133 -10E Table 2: MODULE MARKINGS -13E -133 -10E Timing parameters PC100 CL - tRCD - tRP 2-2-2 2-2-2 2-2-2 PC133 CL - tRCD - tRP 2-2-2 3-3-3 NA Table 3: Part Numbers SYSTEM CONFIGURATION BUS SPEED 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz PARTNUMBER1 MT8LSDT3264AG-13E_ MT8LSDT3264AG(I)-133_ MT8LSDT3264AG-10E_ MT16LSDT6464AG-13E_ MT16LSDT6464AG(I)-133_ MT16LSDT6464AG-10E_ NOTE: 1.
Consult Micron for availability; Industrial Temperature Option available in -133 speed only.
Table 1: Address Table 256MB MODULE 8K 4 (BA0, BA1) 32 Meg x 8 8K (A0–A12) 1K (A0–A9) 1 (S0,S2) 512MB MODULE 8K 4 (BA0, BA1) 32 Meg x 8 8K (A0–A12) 1K (A0–A9) 2 (S0,S2; S1,S3) Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Banks 1.
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