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SY87701L

Part Number	SY87701L
Manufacturer	Micrel Semiconductor
Description	CLOCK AND DATA RECOVERY
Published	Sep 24, 2005
Detailed Description	Micrel, Inc. 3.3V 32-1250Mbps AnyRate® CLOCK AND DATA RECOVERY SY87701L SY87701L Use lower-power SY87701AL for new de...
Datasheet	SY87701L PDF File

Overview

Micrel, Inc.
3.
3V 32-1250Mbps AnyRate® CLOCK AND DATA RECOVERY SY87701L SY87701L Use lower-power SY87701AL for new designs FEATURES ■ Industrial temperature range (–40°C to +85°C) ■ 3.
3V power supply ■ Clock and data recovery from 32Mbps up to 1.
25Gbps NRZ data stream, clock generation from 32Mbps to 1.
25Gbps ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, Fibre Channel and Gigabit Ethernet as well as proprietary applications ■ Two on-chip PLLs: one for clock generation and another for clock recovery ■ Selectable reference frequencies ■ Differential PECL high-speed serial I/O ■ Line receiver input: no external buffering needed ■ Link fault indication ■ 100k ECL compatible I/O ■ Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but NOT recommended for new designs.
) DESCRIPTION The SY87701L is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.
25Gbps NRZ.
The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems.
Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream.
The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio.
On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.
The SY87701L also includes a link fault detection circuit.
All support documentation can be found on Micrel’s web site at www.
micrel.
com.
APPLICATIONS ■ SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24 ■ Fibre Channel, Escon, SMPTE 259 ■ Gigabit Ethernet/Fast Ethernet ■ Proprietary architecture up to 1.
25Gbps BLOCK DIAGRAM PLLR P/N RDINP (PECL) RDINN CD (PECL) REFCLK (TTL) PHASE DETECTOR PHASE/ FREQUENCY DETECTOR 0 1 CHARGE PUMP VCO PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO LINK FAULT DETECTOR 1 0 DIVIDER B...

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