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S16008LK9

SPECtek
Part Number S16008LK9
Manufacturer SPECtek
Description 128Mb :x4 x8 x16 SDRAM
Published Oct 4, 2005
Detailed Description 128Mb: x4, x8, x16 SDRAM 3.3V SYNCHRONOUS DRAM • • • • • • • • • • • Features: Intel PC-100 (3-3-3) or PC133 (3-3-3) c...
Datasheet PDF File S16008LK9 PDF File

S16008LK9
S16008LK9

Overview
128Mb: x4, x8, x16 SDRAM 3.
3V SYNCHRONOUS DRAM • • • • • • • • • • • Features: Intel PC-100 (3-3-3) or PC133 (3-3-3) compatible Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access precharge time Programmable burst lengths: 1, 2, or 4 using Interleaved Burst Addressing Auto Precharge and Auto Refresh modes 64ms, 4,096-cycle refresh quad-row refresh, (15.
6µs/row) Self Refresh mode 1 LVTTL-compatible inputs and outputs Single +3.
3V ±0.
3V power supply The x16 devices are optimized for both single and dual rank DIMM applications.
The x8 devices are optimized for single rank DIMM applications.
Options: Family: SpecTek Memory Configuration: 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) Design ID SDRAM 128 Megabit Design (Call SpecTek Sales for details on availability of “x” placeholders) Voltage and Refresh: 3.
3V, Auto Refresh, 4K refresh 3.
3V, Self or Auto Refresh1, 4K refresh Package Types: 54-pin plastic TSOP (400 mil) 60-ball FBGA (8mm x 16mm) 60-ball FBGA (11mm x 13mm) Timing Types: PC100 (3-3-3) PC133 (3-3-3) Part number example: (For part numbers prior to December 2004, refer to page 9 for decoding.
) Designation: SAA 32M4 16M8 8M16 Yx5x L4 M4 TK FB2 FC2 -8A -75A NOTES: 1.
Only when specified.
Consult Sales 2.
Not available in x16 configuration General Description: The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
Each is internally configured as a quad-bank DRAM.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the ba...


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