DatasheetsPDF.com

74LVT534

NXP
Part Number 74LVT534
Manufacturer NXP
Description 3.3V Octal D-type flip-flop inverting
Published Oct 5, 2005
Detailed Description INTEGRATED CIRCUITS 74LVT534 3.3V Octal D-type flip-flop; inverting (3-State) Product specification Supersedes data of ...
Datasheet PDF File 74LVT534 PDF File

74LVT534
74LVT534

Overview
INTEGRATED CIRCUITS 74LVT534 3.
3V Octal D-type flip-flop; inverting (3-State) Product specification Supersedes data of 1996 Aug 13 IC23 Data Handbook 1998 Feb 19 Philips Semiconductors Philips Semiconductors Product specification 3.
3V Octal D-type flip-flop, inverting (3-State) 74LVT534 FEATURES • 3-State outputs for bus interfacing • Common output enable • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction permitted • No bus current loading when output is tied to 5V bus • Power-up 3-State • Power-up reset • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model resistors to hold unused inputs DESCRIPTION The LVT534 is a high-performance BiCMOS product designed for VCC operation at 3.
3V.
This device is an 8-bit, edge triggered register coupled to eight 3-State output buffers.
The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates.
The state of each D input (one set-up time before the Low-to-High clock transition) is transferred to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation.
When OE is Low, the stored data appears at the outputs.
When OE is High, the outputs are in the High-impedance “off” state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay CP to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 3.
3V VI = 0V or 3.
0V Outputs disabled; VI/O = 0V or 3.
0V Outputs disabled; VCC = 3.
6V TYPICAL 3.
0 3.
5 4 7 0.
13 UNIT ns pF pF...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)