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MT90520

Zarlink Semiconductor
Part Number MT90520
Manufacturer Zarlink Semiconductor
Description 8-Port Primary Rate Circuit Emulation AAL1 SAR
Published Oct 26, 2005
Detailed Description MT90520 8-Port Primary Rate Circuit Emulation AAL1 SAR Data Sheet Features • AAL1 Segmentation and Reassembly device com...
Datasheet PDF File MT90520 PDF File

MT90520
MT90520

Overview
MT90520 8-Port Primary Rate Circuit Emulation AAL1 SAR Data Sheet Features • AAL1 Segmentation and Reassembly device compliant with Circuit Emulation Services (CES) standard (af-vtoa-0078.
000) Supports both Unstructured and Structured Circuit Emulation of 8 independent DS1/E1/STBUS interfaces Supports AAL1 trunking, with up to 128 TDM channels per VC (af-vtoa-0089.
001) Supports CAS transmission and reception in all structured modes of operation Supports simultaneous processing of up to 256 bidirectional Virtual Circuits Supports mixed DS1/E1 operation Supports mixed Unstructured and Structured CES operation Fully flexible DS0 assignment Complete clock recovery solution provided onchip: Synchronous, Adaptive, or Synchronous • • • • VC Look-Up Table January 2004 Ordering Information MT90520AG 456 Pin Plastic BGA -40 to +85°C Residual Time Stamp (SRTS) via 8 independent PLLs • Dual-mode (ATM-end or PHY-end) UTOPIA port operates in Level 1 or Level 2 mode for connection to external PHY or ATM devices with UTOPIA clock rate up to 52 MHz TDM bus provides 8 bidirectional serial streams at 1.
544, 2.
048, or 4.
096 MHz - compatible with Generic (1.
544 Mbps or 2.
048 Mbps) and STBUS (2.
048 Mbps) interfaces Supports master and slave TDM backplane bus clock operation Supports TDM and UTOPIA loopback functions 16-bit microprocessor port, configurable to Motorola or Intel timing Master clock rate of 66.
0 MHz External Synchronous SRAM (ZBT) • • • • • • • • • Segmentation / Reassembly Circular Buffers MT90520 UTOPIA OUTPUT BLOCK TX SAR External Memory Controller Tx/Segmentation (X 8) TDM INPUT BLOCK Clock Management TDM Input Interface Clock Control /Recovery Interface TDM Output Interface Local Memory UTOPIA Interface UTOPIA INPUT BLOCK RX SARs (UDT, SDT, Data) Local Memory PLL TDM OUTPUT BLOCK Rx/Reassembly (X 8) BoundaryScan Logic Microprocessor Interface Logic JTAG Interface 16-bit Microprocessor Interface Figure 1 - MT90520 Block Diagram 1 Zarlink Semiconductor Inc...


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