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MB86613

Fujitsu Media Devices
Part Number MB86613
Manufacturer Fujitsu Media Devices
Description IEEE 1394 Open HCI Controller
Published Oct 28, 2005
Detailed Description FUJITSU SEMICONDUCTOR DATA SHEET DS04-22004-1E ASSP Communication Control IEEE 1394 Open HCI Controller MB86613 s DES...
Datasheet PDF File MB86613 PDF File

MB86613
MB86613

Overview
FUJITSU SEMICONDUCTOR DATA SHEET DS04-22004-1E ASSP Communication Control IEEE 1394 Open HCI Controller MB86613 s DESCRIPTION The MB86613 a high-performance, host-bus (PCI) and serial-bus (1394) controller chip for controlling transfer between the PCI and 1394 buses.
This chip conforms to the PCI Standard Version 2.
1 for PCI control, the IEEE 1394-1995 Standard for 1394 control, and the Open HCI Standard Version 1.
0 for PCI-1394 control.
The MB86613 consists of the PCI/DMA, OHCI, and 1394 blocks.
The PCI/DMA block provides PCI bus protocol control.
The block has the slave function for responding register access from a bus master, the master function for issuing transfer requests from the MB86613 as the bus master, the power management function (compliant with PCI bus power management standard version 1.
0), and the interfaces to BIOS ROM and PCI configuration ROM.
The OHCI block analyzes context programs pre-stored in host memory to store the packet to be sent out from host memory to the FIFO buffer or to store the received packet from the FIFO buffer to host memory.
The 1394 block incorporates the LINK layer module, PHYsical layer module, 1394 transceiver, comparator, and PLL, providing 1394 bus protocol control.
The block converts the packet stored in the FIFO buffer to serial data and send it onto the 1394 bus or converts the packet received from the 1394 bus to parallel data and stores it in the FIFO buffer.
For packet transmission and reception, the chip supports a transfer rate of up to S400.
In addition, the cycle master function is provided for automatic management of isochronous cycles.
The chip reserves 6K bytes of FIFO memory.
The on-chip dual port RAM contains 3K bytes for packet transmission and 3K bytes for packet reception.
The MB86613 uses the 0.
35 micron CMOS process technology, integrating the LINK and PHYsical layer modules on this single chip to reduce the packaging area and power consumption.
The chip has a dual-voltage system to support both ...


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