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KM732V599L

Part Number	KM732V599L
Manufacturer	Samsung Semiconductor
Description	32K X 32Bit Synchronous Pipelined Burst SRAM
Published	Oct 28, 2005
Detailed Description	PRELIMINARY KM732V599A/L Document Title 32Kx36-Bit Synchronous Pipelined Burst SRAM, 3.3V Power Datasheets for 100TQFP ...
Datasheet	KM732V599L PDF File

Overview

PRELIMINARY KM732V599A/L Document Title 32Kx36-Bit Synchronous Pipelined Burst SRAM, 3.
3V Power Datasheets for 100TQFP 32Kx32 Synchronous SRAM Revision History Rev.
No.
Rev.
0.
0 Rev.
1.
0 History Initial draft Final spec release Draft Date Feb.
18.
1997 May.
13.
1997 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics.
SAMSUNG Electronics CO.
, LTD.
reserve the right to change the specifications.
SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device.
If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1- May 1997 Rev 1.
0 PRELIMINARY KM732V599A/L FEATURES • • • • • • • • • • • • • • • • Synchronous Operation.
2Stage Pipelined operation with 4Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD = 3.
3V-5%/+10% Power Supply 5V Tolerant Inputs except I/O Pins Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear burst.
Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A 32Kx32 Synchronous SRAM 32Kx32-Bit Synchronous Pipelined Burst SRAM GENERAL DESCRIPTION The KM732V599A/L is a 1,048,576-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.
It is organized as 32K words of 32 bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW...

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