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TXC-04246

Transwitch
Part Number TXC-04246
Manufacturer Transwitch
Description OC-3 Ethemet Over SONET/SDH Mapper
Published Dec 1, 2005
Detailed Description EtherMap-3 Pt Device OC-3 Ethernet over SONET/SDH Mapper TXC-04246 PRODUCT INFORMATION FEATURES • Eight 10/100 Mbit/s E...
Datasheet PDF File TXC-04246 PDF File

TXC-04246
TXC-04246

Overview
EtherMap-3 Pt Device OC-3 Ethernet over SONET/SDH Mapper TXC-04246 PRODUCT INFORMATION FEATURES • Eight 10/100 Mbit/s Ethernet ports, each using a SMII interface • Single 1000 Mbit/s Ethernet port, using a parallel GMII interface (lead shared with SMII interfaces) • Ethernet Jumbo Frame support, all modes • Ethernet Management interface for control • Low latency throughput performance • 64 ms differential delay compensation • Configurable transmit and receive buffers up to 512 kbytes • Provides IEEE 802.
3 Half Duplex mode on 10/100 Mbit/s and Full Duplex mode on 10/100/1000 Mbit/s Ethernet ports • Provides IEEE 802.
3 Management Statistics (RMON) • Ethernet frame encapsulation/decapsulation protocols: • ITU-T G.
7041, Generic Framing Procedure (GFP) • ITU-T X.
86/X.
85, Link Access Procedure SDH (LAPS) • ITU-T Q.
922, Link Access Procedure Frame Mode (LAPF) • RFC1662/3518, PPP Bridging Control Protocol (BCP) • Performs mapping/demapping of encapsulated Ethernet frames into/from low order (VT1.
5 SPE/VT2 SPE/VC-11/ VC-12) and high order (STS-1 SPE/VC-3) virtually concatenated payloads • Performs mapping/demapping of encapsulated Ethernet frames into/from a single contiguous concatenated (STS-3cSPE/VC-4) payload or a single Low/High order (VT1.
5/VT2/ VC-11/VC-12/STS-1/VC-3) payload • On-chip LCAS processing (ITU-T G.
7042) for low and high order virtual concatenated payloads • Glueless interface to external 64/128/256 Mbit SDRAM • Low Order POH and Pointer processing for 84/63 VT1.
5/ VT2/TU-11/TU-12 and 3 TU-3 • High Order POH processing for STS-1 SPE/VC-3/STS-3c SPE/VC-4 • Byte-wide 19 MHz parallel Add and Drop Telecom Bus interfaces • Per-port Ethernet side and SONET/SDH system side loopback for system level diagnostics • 16-bit wide microprocessor interface, selectable between Motorola or Intel • Boundary scan (IEEE 1149.
1 standard) • + 3.
3V and +1.
8V power supplies, 5V tolerant I/O leads • 400-lead plastic ball grid array package (PBGA, 27 mm x 27 mm) • Device Driver D...


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