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KM416S1021C

Part Number	KM416S1021C
Manufacturer	Samsung Semiconductor
Description	512K x 16-Bit x 2-Bank SDRAM
Published	Dec 5, 2005
Detailed Description	KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface FEATURES • JEDEC standard 3.3V power supply • SS...
Datasheet	KM416S1021C PDF File

Overview

KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface FEATURES • JEDEC standard 3.
3V power supply • SSTL_3 (Class II) compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) Preliminary CMOS SDRAM GENERAL DESCRIPTION The KM416S1021C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SA...

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