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MC54HC4060

Motorola
Part Number MC54HC4060
Manufacturer Motorola
Description 14-Stage Binary Ripple Counter
Published Dec 5, 2005
Detailed Description MOTOROLA SEMICONDUCTOR TECHNICAL DATA 14-Stage Binary Ripple Counter with Oscillator High–Performance Silicon–Gate CMO...
Datasheet PDF File MC54HC4060 PDF File

MC54HC4060
MC54HC4060

Overview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 14-Stage Binary Ripple Counter with Oscillator High–Performance Silicon–Gate CMOS The MC54/74HC4060 is identical in pinout to the standard CMOS MC14060B.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally.
The output of each flip–flop feeds the next, and the frequency at each output is half that of the preceding one.
The state of the counter advances on the negative–going edge of Osc In.
The active–high Reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
• • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No.
7A • Chip Complexity: 390 FETs or 97.
5 Equivalent Gates MC54/74HC4060 J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648–08 16 1 DT SUFFIX TSSOP PACKAGE CASE 948F–01 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDT Ceramic Plastic TSSOP PIN ASSIGNMENT Q12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q10 Q8 Q9 RESET OSC IN OSC OUT 1 OSC OUT 2 LOGIC DIAGRAM OSC OUT 1 10 OSC OUT 2 9 7 5 OSC IN 11 4 6 14 13 15 1 2 3 12 PIN 16 = VCC PIN 8 = GND Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 X Clock Q13 Q14 Q6 Q5 Q7 Q4 GND FUNCTION TABLE Reset L L H Output State No Change Advance to Next State All Outputs are Low RESET 10/95 © Motorola, Inc.
1995 1 REV 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎ...


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