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EBD52UD6ADSA-E

Part Number	EBD52UD6ADSA-E
Manufacturer	Elpida Memory
Description	512MB DDR SDRAM SO-DIMM
Published	Dec 15, 2005
Detailed Description	DATA SHEET 512MB DDR SDRAM SO-DIMM EBD52UD6ADSA-E (64M words × 64 bits, 2 Ranks) Description The EBD52UD6ADSA is 64M wo...
Datasheet	EBD52UD6ADSA-E PDF File

Overview

DATA SHEET 512MB DDR SDRAM SO-DIMM EBD52UD6ADSA-E (64M words × 64 bits, 2 Ranks) Description The EBD52UD6ADSA is 64M words × 64 bits, 2 ranks Double Data Rate (DDR) SDRAM Small Outline Dual In-line Memory Module, mounting 8 pieces of 512M bits DDR SDRAM sealed in TSOP package.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each TSOP on the module board.
Features • 200-pin socket type small outline dual in line memory module (SO-DIMM)  PCB height: 31.
75mm  Lead pitch: 0.
6mm  Lead-free • 2.
5V power supply • Data rate: 333Mbps/266Mbps (max.
) • 2.
5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs, outputs and DM are synchronized with DQS • 4 internal banks for concurrent operation (Components) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.
5 • Refresh cycles: (8192 refresh cycles /64ms)  7.
8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh Document No.
E0604E10 (Ver.
1.
0) Date Published October 2004 (K) Japan URL: http://www.
elpida.
com ...

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