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17512LJC

Xilinx
Part Number 17512LJC
Manufacturer Xilinx
Description XC17512LJC
Published Dec 30, 2005
Detailed Description 0 R XC1700E and XC1700L Series Configuration PROMs 0 8 DS027 (v3.1) July 5, 2000 Product Specification Features • O...
Datasheet PDF File 17512LJC PDF File

17512LJC
17512LJC

Overview
0 R XC1700E and XC1700L Series Configuration PROMs 0 8 DS027 (v3.
1) July 5, 2000 Product Specification Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions XC17128E/EL, XC17256E/EL, XC1701 and XC1700L series support fast configuration Low-power CMOS Floating Gate process XC1700E series are available in 5V and 3.
3V versions XC1700L series are available in 3.
3V only Available in compact plastic packages: 8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP.
Programming support by leading programmer manufacturers.
Design support using the Xilinx Alliance and Foundation series software packages.
Guaranteed 20 year life data retention Description The XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
Once configured, it disables the PROM.
When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex for...


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