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BUS-61563-xxxx

Part Number	BUS-61563-xxxx
Manufacturer	Data Device
Description	Advanced Integrated MUX Hybrid
Published	Jan 2, 2006
Detailed Description	m o MIL-STD-1553 ADVANCED INTEGRATED .c U MUX (AIM ) HYBRID SO L 4 A E E t S E e S GUID ’ R E S U e h DESCRIPTION S FEAT...
Datasheet	BUS-61563-xxxx PDF File

Overview

m o MIL-STD-1553 ADVANCED INTEGRATED .
c U MUX (AIM ) HYBRID SO L 4 A E E t S E e S GUID ’ R E S U e h DESCRIPTION S FEATURES a • Fully Intergrated Terminal at Including: .
D –Dual Transceiver w –BC/RT/MT Protocol w –Memory Management Unit w –Processor lnterface Logic DDC’s BUS-61553 Advanced Integrated Mux (AIM) Hybrid is a complete MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT) device.
Packaged in a single 78-pin DIP package, the BUS-61553 contains dual low-power transceivers, complete BC/RT/MT protocol logic, a MIL-STD-1553-to-host interface unit and 8K x 16 RAM.
Using an industry standard dual transceiver and standard status and control signals, the BUS-61553 simplifies system integration at both the MIL-STD-1553 and host processor interface levels.
All 1553 operations are controlled through the CPU access to the BUS-61553 BUS-25679 8 1 DATA BUS A 2 4 3 TRANSFORMER A BUS-25679 8 DATA BUS B 4 1 2 3 m o .
c U 4 t e e h S a t a .
D w w w –8K x 16 RAM The BUS-61553 operates over the full military -55°C to +125°C temperature range.
Available screened to MIL-PRF-38534, the BUS-61553 is ideal for demanding military and industrial microprocessor-to-1553 interface applications.
shared 8K x 16 RAM.
To ensure maximum design flexibility, memory control lines are provided for attaching external RAM to the BUS-61553 address and data buses and for disabling internal memory; the total combined memory space can be expanded to 64K x 16.
All 1553 transfers are entirely memory-mapped; thus the CPU interface requires minimal hardware and/or software support.
• CMOS and Bipolar Technologies • Internal Interrupt Status and Time Tag Registers • High Reliability • 883B Processing Available TRANSCEIVER A TX INH TX CLOCK IN RX CHANNEL A ENCODER/ DECODER MEMORY TIMING RX CPU TIMING MSTRCLR SELECT STRBD READYD RD/WR MEM/REG EXTEN EXTLD INT 768 µs TIME OUT PROTOCOL CONTROLLER CONTENTION RESOLVER INTERRUPT GENERATOR TX INH TX TRANSFORMER ...

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