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CY3120

Cypress Semiconductor
Part Number CY3120
Manufacturer Cypress Semiconductor
Description CPLD Development Software for PC
Published Jan 4, 2006
Detailed Description 0 Features • VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following featur...
Datasheet PDF File CY3120 PDF File

CY3120
CY3120

Overview
0 Features • VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features: — Designs are portable across multiple devices and/or EDA environments w w — Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design w .
D a S a t e e h U 4 t .
m o c CY3120 Warp® CPLD Development Software for PC — User selectable speed and/or area optimization on a block-by-block basis — Perfect communication between synthesis and fitting — Automatic selection of optimal flip-flop type (D type/T type) — Automatic pin assignment • Supports all Cypress Programmable Logic Devices — PSI™ (Programmable Serial Interface) — Delta39K™ CPLDs — Quantum38K™ CPLDs — Ultra37000™ CPLDs — FLASH370i™ CPLDs — MAX340™ CPLDs — Support for functions and libraries facilitating modular design methodology • IEEE Standard 1076 and 1164 VHDL synthesis supports: — Enumerated types — Operator overloading — For.
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Generate statements — Integers • IEEE Standard 1364 Verilog synthesis supports: — Reduction and conditional operators — Blocking and non-blocking procedural assignments — While loops — Integers • Several design entry methods support high-level and low-level design descriptions: — Behavioral VHDL and Verilog (IF.
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THEN.
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ELSE; CASE.
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) — Boolean — Aldec Active-HDL™ FSM graphical Finite State Machine editor — Structural Verilog and VHDL — Designs can include multiple entry methods (but only one HDL language) in a single design.
• UltraGen™ Synthesis and Fitting Technology: — Infers “modules” such as adders, comparators, etc.
, from behavioral descriptions and replaces them with circuits pre-optimized for the target device.
w w w .
D t a S a e h — Industry standard PLDs (16V8, 20V8, 22V10) • VHDL and Verilog timing model output for use with third-party simulators • Timing simulation provided by Active-HDL™ Sim Release 3.
3 from Aldec — Graphical waveform simulator — Entry and modification of on-s...


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