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IDT72V70210

Integrated Device Technology
Part Number IDT72V70210
Manufacturer Integrated Device Technology
Description 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
Published Jan 11, 2006
Detailed Description 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 FEATURES: • • IDT72V70210 32 serial input and output strea...
Datasheet PDF File IDT72V70210 PDF File

IDT72V70210
IDT72V70210


Overview
3.
3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024 FEATURES: • • IDT72V70210 32 serial input and output streams 1,024 x 1,024 channel non-blocking switching at 2.
048 Mb/s • Per-channel Variable Delay Mode for low-latency applications • Per-channel Constant Delay Mode for frame integrity applications • Automatic identification of ST-BUS® and GCI serial streams • Automatic frame offset delay measurement • Per-stream frame delay offset programming • Per-channel high impedance output control • Per-channel processor mode to allow microprocessor writes to TX streams • Direct microprocessor access to all internal memories • Memory block programming for quick set-up • IEEE-1149.
1 (JTAG) Test Port • Internal Loopback for testing • · Available in 144-pin Ball Grid Array (BGA) and 144-pin Thin Quad • • Flatpack (TQFP) packages Operating Temperature Range -40°C to +85°C 3.
3V I/O with 5V tolerant inputs and TTL compatible outputs DESCRIPTION: The IDT72V70210 has a non-blocking switch capacity of 1,024 x 1,024 channels at 2.
048 Mb/s.
With 32 inputs and 32 outputs, programmable per stream control, and a variety of operating modes the IDT72V70210 is designed for the TDM time slot interchange function in either voice or data applications.
Some of the main features of the IDT72V70210 are low power 3.
3 Volt operation, automatic ST-BUS®/GCI sensing, memory block programming, simple microprocessor interface, one cycle direct internal memory accesses, JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, internal loopback, output enable, and Processor Mode.
FUNCTIONAL BLOCK DIAGRAM Vcc GND RESET TMS TDI TDO TCK TRST ODE Test Port RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 Loopback Output MUX Data Memory Receive Serial Data Streams Transmit Serial Data Streams Internal Registers Connection Memory TX0 TX...



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