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MR16R1622AF0

Samsung semiconductor
Part Number MR16R1622AF0
Manufacturer Samsung semiconductor
Description (MR1xR1622(4/8/G)AF0) (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die
Published Jan 19, 2006
Detailed Description MR16R1622(4/8/G)AF0 MR18R1622(4/8/G)AF0(1) Change History Version 1.1 (August 2001) * First copy. * Based on the 1.0ver ...
Datasheet PDF File MR16R1622AF0 PDF File

MR16R1622AF0
MR16R1622AF0


Overview
MR16R1622(4/8/G)AF0 MR18R1622(4/8/G)AF0(1) Change History Version 1.
1 (August 2001) * First copy.
* Based on the 1.
0ver Rambus 256/288Mbit RIMM Module Datasheet Version 1.
2 (February 2002) * Add 1066-35 binning Version 1.
3 (April 2002) * Add 800-40 and 1066-32 binning * Modify ∆TPD Value of AC electrical specifications * Modify the Values of AC electrical specifications for RIMM Module Version 1.
4 (July 2002) * Add 1066-32 512MB (16d RIMM Module) etc.
Page 0 Version 1.
4 July 2002 MR16R1622(4/8/G)AF0 MR18R1622(4/8/G)AF0(1) (16Mx16)*2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.
5V (16Mx18)*2(4/8/16)pcs RIMM Module based on 288Mb A-die, 32s banks,16K/32ms Ref, 2.
5V Overview The RIMM module is a general purpose high- performance memory module suitable for use in a broad range of applications including computer memory, personal computers, workstations and other applications where high bandwidth and low latency are required.
The RIMM module consists of 256/288Mb devices.
These are extremely high-speed CMOS DRAMs organized as 16M words by 16 or 18 bits.
The use of Rambus Signaling Level (RSL) technology permits up to 1066 MHz transfer rates while using conventional system and board design technologies.
RDRAM devices are capable of sustained data transfers at 0.
94 ns per two bytes (7.
5ns per 16 bytes).
The RDRAM architecture enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed, memory transactions.
The separate control and data buses with independent row and column control yield over 95% bus efficiency.
The RDRAM device's 32-bank architecture supports up to four simultaneous transactions per device.
RDRAM Key Timing Parameters/Part Numbers The following table lists the frequency and latency bins available for RIMM modules.
Table 1: Part Number by Freq.
& Latency Speed Organization Bin tRAC I/O (Row Freq.
Access (MHz) Time) ns 800 800 1066 1066 800 800 1066 1066 800 800 1066 1066 800 800 40 45 32P 32 4...


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