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CYP25G01K100

Cypress Semiconductor
Part Number CYP25G01K100
Manufacturer Cypress Semiconductor
Description 2.5Gbps Programmable Serial Interface
Published Feb 8, 2006
Detailed Description Features w w • High-speed (HS) Programmable Serial Interface™ (PSI™) • 2.48- to 2.5-Gbps serial signaling rate • Full...
Datasheet PDF File CYP25G01K100 PDF File

CYP25G01K100
CYP25G01K100

Overview
Features w w • High-speed (HS) Programmable Serial Interface™ (PSI™) • 2.
48- to 2.
5-Gbps serial signaling rate • Full Bellcore and ITU jitter compliance • Flexible parallel-to-serial conversion in transmit path • Flexible serial-to-parallel conversion in receive path • Multiple selectable loopback/loop-through modes • 100K of usable gates of CPLD logic • 240K of integrated memory — 192K of synchronous or asynchronous SRAM w .
D at h S a t e e 4U .
m o c 2.
5-Gbps Programmable Serial Interface™ — Circuit board traces — Backplane links — Box-to-box links — Chip-to-chip communication • Extremely flexible clocking options — Four global clocks — Up to 192 additional product term clocks — Clock polarity at every register • Carry chain logic for fast and efficient arithmetic operations • JTAG programming interface with boundary scan support • Power-saving mode • Supported standards: — SONET OC-48 and SDH STM-16 — InfiniBand™ — Custom 2.
5-Gbps interface • • • • • • • • — 48K of true Dual-Port or FIFO RAM Internal transmit and receive phase-locked loops (PLLs) Logic dedicated Spread Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial input with internal termination and DC-restoration Differential CML serial output with source-matched impedance of 50Ω 240 user-programmable I/Os Any Volt™ I/O interface — Programmable as 1.
5V, 1.
8V, 2.
5V, 3.
3V Multiple I/O standards — LVCMOS, LVTTL, 3.
3V PCI, SSTL2(I-II), SSTL3(I-II), HSTL(I-IV), and GTL+ — Fully PCI-compliant (Rev.
2.
2) • Direct interface to standard fiber-optic modules • Designed to drive: — Fiberoptic modules — Copper cables 2.
5-Gbps PSI Family—Standards Supported PSI Device SONET/SDH High Speed CYS25G01K100 CYP25G01K100 2.
5-Gbps PSI Family—General Features Device Typical Gates Macrocells 1536 Cluster Memory (Kbits) 192 Channel Memory (Kbits) 48 Maximum UserProgrammable I/O 240 Package Offering w w w .
D t a S a X e h Development Software • Warp® — IEEE 1076/1164 VHDL o...


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