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MCF5407

Motorola
Part Number MCF5407
Manufacturer Motorola
Description Microprocessor
Published Feb 18, 2006
Detailed Description Advance Information MCF5407PB/D Rev. 3.3, 2/2003 MCF5407 Integrated ColdFire® Microprocessor Product Brief w w w .D...
Datasheet PDF File MCF5407 PDF File

MCF5407
MCF5407

Overview
Advance Information MCF5407PB/D Rev.
3.
3, 2/2003 MCF5407 Integrated ColdFire® Microprocessor Product Brief w w w .
D at h S a t e e 4U .
m o c This document is an overview of the MCF5407 ColdFire processor, focusing on feature enhancements over the MCF5307.
It includes general descriptions of features and of the various modules incorporated in the MCF5407.
It describes the V4 programming model as it is implemented in the MCF5407.
1.
1 • • • • • • • • • • • • Features The MCF5407 integrated microprocessor combines a Version 4 ColdFire processor core with the following components, as shown in Figure 1: Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte data cache Two, 2-Kbyte on-chip SRAMs Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller for synchronous and asynchronous DRAM Four-channel DMA controller Two general-purpose timers Two UARTs, one that supports synchronous operations I2C™ interface Parallel I/O interface System integration module (SIM) w w w .
D t a S a e h t e U 4 .
c m o Designed for embedded control applications, the MCF5407 delivers 316 Dhrystone MIPS at 220 MHz or 233 Dhrystone MIPS at 162 MHz.
w w w .
D at h S a t e e 4U .
m o c Features V4 COLDFIRE PROCESSOR COMPLEX JTAG Branch Logic 8-Entry Branch Cache IAG IC1 IC2 IED Instruction Fetch Pipeline (IFP) .
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128-Entry Prediction Table CCR Ten-Instruction FIFO Buffer Operand Execution Pipeline (OEP) LIFO Return Stack DIV Debug Module ÷2 PSTCLK DS AG OC1 OC2 EX MAC DA GeneralPurpose Registers A0–A7 D0–D7 31 0 31 0 SRAM Controller RAMBAR0 RAMBAR1 2-Kbyte SRAM0 2-Kbyte SRAM1 Local Memory Data Bus CLKIN (to on-chip peripherals) Local Memory Instruction Bus Harvard Cache Controller CACR ACR2 ACR3 ACR0 ACR1 8-Kbyte Data Cache CLKIN RSTI PLL Xn PCLK RSTO 16-Kbyte Instruction Cache 31 0 4-Entry Store Buffer SYSTEM INTEGRATION MODULE (SIM) PLL Control PLL DMA Parallel Port P...


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