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18F4550

Microchip Technology
Part Number 18F4550
Manufacturer Microchip Technology
Description PIC18F4550
Published Mar 7, 2006
Detailed Description www.DataSheet4U.com PIC18F2455/2550/4455/4550 28/40/44-Pin High-Performance, Enhanced Flash USB Microcontrollers with n...
Datasheet PDF File 18F4550 PDF File

18F4550
18F4550

Overview
www.
DataSheet4U.
com PIC18F2455/2550/4455/4550 28/40/44-Pin High-Performance, Enhanced Flash USB Microcontrollers with nanoWatt Technology Universal Serial Bus Features: • USB V2.
0 Compliant SIE • Low-speed (1.
5 Mb/s) and full-speed (12 Mb/s) • Supports control, interrupt, isochronous and bulk transfers • Supports up to 32 endpoints (16 bidirectional) • 1-Kbyte dual access RAM for USB • On-board USB transceiver with on-chip voltage regulator • Interface for off-chip USB transceiver • Streaming Parallel Port (SPP) for USB streaming transfers (40/44-pin devices only) Peripheral Highlights: • • • • High current sink/source: 25 mA/25 mA Three external interrupts Four Timer modules (Timer0 to Timer3) Up to 2 Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max.
resolution 6.
25 ns (TCY/16) - Compare is 16-bit, max.
resolution 100 ns (TCY) - PWM output: PWM resolution is 1 to 10-bit Enhanced Capture/Compare/PWM (ECCP) module: - Multiple output modes - Selectable polarity - Programmable dead-time - Auto-Shutdown and Auto-Restart Addressable USART module: - LIN bus support Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ (all 4 modes) and I2C™ Master and Slave modes 10-bit, up to 13-channels Analog-to-Digital Converter module (A/D) with programmable acquisition time Dual analog comparators with input multiplexing • Power Managed Modes: • • • • • • • • Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.
8 µA typical Sleep current down to 0.
1 µA typical Timer1 oscillator: 1.
1 µA typical, 32 kHz, 2V Watchdog Timer: 2.
1 µA typical Two-Speed Oscillator Start-up • • • • Special Microcontroller Features: • C compiler optimized architecture with optional extended instruction set • 100,000 erase/write cycle Enhanced Flash program memory typical • 1,000,000 erase/write cycle data EEPROM memory typical • Flash/data EEPROM retention: > 40 years • Self-programmable under software control • ...


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