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MT48LC4M32LFF5

Micron Technology
Part Number MT48LC4M32LFF5
Manufacturer Micron Technology
Description (MT48xx8Mxxxx) SYNCHRONOUS DRAM
Published Mar 18, 2006
Detailed Description 128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAM Features • Temperature Compensated Self Refresh (TCSR) • Fully synchronou...
Datasheet PDF File MT48LC4M32LFF5 PDF File

MT48LC4M32LFF5
MT48LC4M32LFF5


Overview
128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAM Features • Temperature Compensated Self Refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes • Self Refresh Mode; standard and low power • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Low voltage power supply • Partial Array Self Refresh power-saving mode OPTIONS MARKING LC G V MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF, MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC, MT48V4M32LFF5 For the latest data sheet, please refer to the Micron Web site: www.
micron.
com/dramds Figure 1: Pin Assignment (Top View) 54-Ball FBGA 1 A B C D E F G H J VSS 2 DQ15 3 VSSQ 4 5 DQ14 DQ13 VDDQ DQ12 DQ11 DQ10 DQ9 UDQM • VDD/VDDQ 3.
3V/3.
3V 3.
0V/3.
0V1 2.
5V/2.
5V – 1.
8V • Configurations 8 Meg x 16 (2 Meg x 16 x 4 banks) 4 Meg x 32 (1 Meg x 32 x 4 banks) • Package/Ball out 54-ball FBGA (8mm x 9mm)2 54-ball FBGA (8mm x 9mm)2 Lead-Free 54-ball VFBGA (8mm x 8mm)2 54-ball VFBGA (8mm x 8mm)2 Lead-Free 90-ball FBGA (11mm x 13mm)3 90-ball FBGA (11mm x 13mm)3 Lead-Free 90-ball VFBGA (8mm x 13mm)3 90-ball VFBGA (8mm x 13mm)3 Lead-Free • Timing (Cycle Time) 8ns @ CL = 3 (125 MHz) 10ns @ CL = 3 (100 MHz) • Temperature Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Extended (-25°C to +75°C) w w w .
D t a 8M16 4M32 FF BF F4 B4 FC BC F5 B5 S a e h NC/A12 t e DQ8 NC A8 A7 VSS A5 CLK U 4 VDDQ VSS CKE A9 A6 A4 VSSQ .
c m o 6 7 VDDQ VSSQ VDDQ VSSQ VDD CAS# BA0 A0 8 9 VDD DQ0 DQ2 DQ1 DQ4 DQ3 DQ6 DQ5 LDQM DQ7 RAS# WE# A11 BA1 CS# A1 A10 A3 A2 VDD Top View (Ball Down) 8 Meg x 16 Configuration Refresh Count Row Addressing Bank Addressing Column Addressin...


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