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ST20450

ST Microelectronics
Part Number ST20450
Manufacturer ST Microelectronics
Description 32-BIT MICROPROCESSOR
Published Apr 13, 2006
Detailed Description ( DataSheet : www.DataSheet4U.com ) ® ST20450 32 BIT MICROPROCESSOR ENGINEERING DATA FEATURES s Enhanced 32-bit CPU ...
Datasheet PDF File ST20450 PDF File

ST20450
ST20450

Overview
( DataSheet : www.
DataSheet4U.
com ) ® ST20450 32 BIT MICROPROCESSOR ENGINEERING DATA FEATURES s Enhanced 32-bit CPU • 0 to 40 MHz processor clock • 32 MIPS at 40 MHz • fast integer/bit operations s System Services 32-bit Processor 16 Kbytes on-chip SRAM • 160 Mbytes/s maximum bandwidth s Programmable memory interface Timers OS-Link OS-Link ST20 Bus • 4 separately configurable regions • 8/16/32-bits wide • support for mixed memory • 2 cycle external access • support for page mode DRAM s OS-Link OS-Link Event 16 Kbytes SRAM Serial communications • 4 OS-Links • 5/10/20 Mbits/s Link0, 10/20 Mbits/s Link1-3 • Event channel s Interrupt External Memory Interface Interrupt Vectored interrupt subsystem • Fully prioritized interrupts • 8 levels of preemption • 500 ns response time s .
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Interrupt Power management • low power operation • power down mode s Professional toolset support • ANSI C compiler and libraries • INQUEST advanced debugging tools s Technology • 0 to 40 MHz processor clock • 0.
5 micron process technology • 3 V operation (3 V outputs/bi-directionals, 5 V inputs) s s APPLICATIONS s Global positioning by satellite (GPS) receivers s ISDN terminals s ATM networks s Set top terminals s Industrial control s Imaging systems 208 pin PQFP package Test Access Port www.
DataSheet4U.
com September 1995 The information in this datasheet is subject to change www.
DataSheet4U.
com 42 1626 04 1/106 ST20450 bug list Trap enables word This register contains the word which encodes the trap enable and global interrupt masks.
This should be ANDed with the existing masks to allow the trap handler to disable various events while it runs.
However, currently the trap enables word overwrites the existing enables.
With this implementation a trap must disable all other trap groups to ensure correct execution, this increases the difficulty of writing nested trap handlers.
Analysing high priority processes If the machine is running a high priority process b...


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