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EDD2504AKTA

Part Number	EDD2504AKTA
Manufacturer	Elpida Memory
Description	256M bits DDR SDRAM (64M words x 4 bits)
Published	May 7, 2006
Detailed Description	( DataSheet : www.DataSheet4U.com ) DATA SHEET 256M bits DDR SDRAM EDD2504AKTA (64M words × 4 bits) Description The ED...
Datasheet	EDD2504AKTA PDF File

Overview

( DataSheet : www.
DataSheet4U.
com ) DATA SHEET 256M bits DDR SDRAM EDD2504AKTA (64M words × 4 bits) Description The EDD2504AK is a 256M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 4 bits × 4 banks.
Read and write operations are performed at the cross points of the CK and the /CK.
This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Pin Configurations /xxx indicates active low signal.
66-pin Plastic TSOP(II) VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Top view) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS Features • Power supply : VDDQ = 2.
5V ± 0.
2V : VDD = 2.
5V ± 0.
2V • Data rate: 333Mbps/266Mbps (max.
) • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs, outputs, and DM are synchronized with DQS • 4 internal banks for concurrent operation • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Auto precharge option for each burst access • SSTL_2 compatible I/O • Programmable burst length (BL): 2, 4, 8 • Programmable /CAS latency (CL)...

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