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THC63LVDM83R

THine Electronics
Part Number THC63LVDM83R
Manufacturer THine Electronics
Description (THC63LVDM63R / THC63LVDM83R) Reduced Swing LVDS 24-Bit / 18-Bit Color Host LCD Panel Interface
Published Aug 8, 2006
Detailed Description www.DataSheet4U.com THC63LVDM83R/THC63LVDM63R_Rev2.0 THC63LVDM83R/THC63LVDM63R REDUCED SWING LVDS 24Bit/18Bit COLOR HO...
Datasheet PDF File THC63LVDM83R PDF File

THC63LVDM83R
THC63LVDM83R

Overview
www.
DataSheet4U.
com THC63LVDM83R/THC63LVDM63R_Rev2.
0 THC63LVDM83R/THC63LVDM63R REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM83R transmitter converts 28bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.
At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 595Mbps per LVDS channel.
Also available is THC63LVDM63R that converts 21bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream.
Both transmitters can be programmed reduced swing LVDS through a dedicated pin for low power consumption and EMI.
Features • 28:4 Data channel compression at up to 298 Megabytes per sec throughput • Wide dot clock range: 20-85MHz suited for VGA, • • Support Reduced swing LVDS for Low EMI • 200mV swing LVDS/350mV swing LVDS • • • • • • • • selectable Support Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No external components Single 3.
3V supply with 125mW(TYP) Power-Down Mode Low profile 56 or 48 Lead TSSOP Package SVGA, XGA and SXGA Narrow bus (10 lines or 8 lines) reduces cable size Clock Edge Programmable Improved Replacement for the National DS90C383 or DS90C363 DataSheet4U.
com Block Diagram DataShee CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 TD0-6 7 7 7 7 THC63LVDM83R DATA (LVDS) TA +/TB +/TC +/TD +/(140-595Mbit/On Each LVDS Channel) CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 7 7 7 THC63LVDM63R DATA (LVDS) TA +/TB +/TC +/- TTL PARALLEL TO SERIAL TTL PARALLEL TO SERIAL TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS (140-595Mbit/On Each LVDS Channel) TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS PLL TCLK +/CLOCK (LVDS) 20-85MHz PLL TCLK +/CLOCK (LVDS) 20-85MHz DataSheet4U.
com Copyright 2001-2003 THine Electronics, Inc.
All rights reserved 1 THi...


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