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TC74AC573P

Toshiba Semiconductor
Part Number TC74AC573P
Manufacturer Toshiba Semiconductor
Description Octal D-Type Latch
Published Aug 25, 2006
Detailed Description TC74AC573P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC573P, TC74AC573F, TC74AC573FT Octal D-...
Datasheet PDF File TC74AC573P PDF File

TC74AC573P
TC74AC573P

Overview
TC74AC573P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC573P, TC74AC573F, TC74AC573FT Octal D-Type Latch with 3-State Output The TC74AC573 is an advanced high speed CMOS OCTAL LATCH fabricated with silicon gate and double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
These 8-bit D-type latches are controlled by a latch enable input (LE) and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high impedance state.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features • High speed: tpd = 6.
0 ns (typ.
) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.
5 V • Pin and function compatible with 74F573 TC74AC573P TC74AC573F TC74AC573FT Weight DIP20-P-300-2.
54A SOP20-P-300-1.
27A TSSOP20-P-0044-0.
65A : 1.
30 g (typ.
) : 0.
22 g (typ.
) : 0.
08 g (typ.
) Start of commercial production 1988-10 1 2014-03-01 Pin Assignment TC74AC573P/F/FT IEC Logic Symbol OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE OE (1) EN LE (11) C1 D0 (2) 1D D1 (3) D2 (4) D3 (5) D4 (6) D5 (7) D6 (8) D7 (9) (top view) Truth Table Inputs OE LE D H X X L L X L H L L H H Output Q Z Qn L H X: Don’t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram (19) Q0 (18) Q1 (17) Q2 (16) Q3 (15) Q4 (14) Q5 (13) Q6 (12) Q7 11 LE D0 2 D D1 3 D D2 4 D D3 5 D D4 6 D D5 7 D D6 8 D D7 9 D Q Q Q Q Q Q Q Q L L L L L L L L 1 OE 19 Q0 18 Q1 17 Q2...


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