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NT5DS32M8BW

Part Number	NT5DS32M8BW
Manufacturer	Nanya Techology
Description	(NT5DSxxMxBx) 256Mb DDR SDRAM
Published	Sep 24, 2006
Detailed Description	www.DataSheet4U.com NT5DS64M4BT NT5DS64M4BW NT5DS32M8BT NT5DS32M8BW NT5DS16M16BT NT5DS16M16BW 256Mb DDR SDRAM Features...
Datasheet	NT5DS32M8BW PDF File

Overview

www.
DataSheet4U.
com NT5DS64M4BT NT5DS64M4BW NT5DS32M8BT NT5DS32M8BW NT5DS16M16BT NT5DS16M16BW 256Mb DDR SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR333 DDR266B (-6K) * (-75B) 2 133 100 2.
5 166 133 * -6K also meets DDR266A Spec (MHz-CL-tRCD-tRP = 133-2-3-3) CAS Latency • • • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2, 2.
5 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.
8µs Maximum Average Periodic Refresh Interval 2.
5V (SSTL_2 compatible) I/O VDDQ = 2.
5V ± 0.
2V VDD = 2.
5V ± 0.
2V -6K Speed sort: Supports PC2700/PC2100 modules -75B Speed sort: Supports PC2100 modules Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
It is internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations.
An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate As with standard SDRAMs, the pipelined, multibank architecDataSheet4U.
com DataShee architecture is essentially a 2n prefetch architecture with an ture of DDR SDRAMs allows for concurrent operation, interface designed to transfer two data words per clock cycle thereby providing high effective bandwidth by...

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