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MC74AC534

Motorola
Part Number MC74AC534
Manufacturer Motorola
Description OCTAL D-TYPE FLIP-FLOP
Published Oct 14, 2006
Detailed Description www.DataSheet4U.com MC74AC534 MC74ACT534 Octal DĆType FlipĆFlop With 3ĆState Outputs The MC74AC534/74ACT534 is a high-s...
Datasheet PDF File MC74AC534 PDF File

MC74AC534
MC74AC534

Overview
www.
DataSheet4U.
com MC74AC534 MC74ACT534 Octal DĆType FlipĆFlop With 3ĆState Outputs The MC74AC534/74ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
A buffered Clock (CP) and Output Enable (OE) are common to all flip flops.
The ′AC/ACT534 is the same as the ′AC/ACT374 except that the outputs are inverted.
• Edge-Triggered D-Type Inputs • Buffered Positive Edge-Triggered Clock • 3-State Outputs for Bus Oriented Applications VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 N SUFFIX CASE 738-03 PLASTIC OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND DW SUFFIX CASE 751D-04 PLASTIC PIN NAMES D0–D7 CP OE O0–O7 Data Inputs Clock Pulse Input 3-State Output Enable Input Complementary 3-State Outputs LOGIC SYMBOL 3 4 7 8 13 14 17 18 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CP OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19 FACT DATA DataSheet 4 U .
com 5-1 www.
DataSheet4U.
com MC74AC534 MC74ACT534 FUNCTIONAL DESCRIPTION The MC74AC534/74ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs.
The buffered clock and buffered Output Enable are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the flip-flops.
LOGIC DIAGRAM D0 CP CP Q D CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7 OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS* Symbol V...


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