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IDT2308

Part Number	IDT2308
Manufacturer	Integrated Device
Description	3.3V ZERO DELAY CLOCK MULTIPLIER
Published	Oct 21, 2006
Detailed Description	www.DataSheet4U.com IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO D...
Datasheet	IDT2308 PDF File

Overview

www.
DataSheet4U.
com IDT2308 3.
3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.
3V ZERO DELAY CLOCK MULTIPLIER FEATURES: DESCRIPTION: IDT2308 • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clock input • Output Skew <200 ps • Low jitter <200 ps cycle-to-cycle • 1x, 2x, 4x output options (see table): – IDT2308-1 1x – IDT2308-2 1x, 2x – IDT2308-3 2x, 4x – IDT2308-4 2x – IDT2308-1H, -2H, and -5H for High Drive • No external RC network required • Operates at 3.
3V VDD • Available in SOIC and TSSOP packages The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier.
It is designed to address high-speed clock distribution and multiplication applications.
The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308 has two banks of four outputs each that are controlled via two select addresses.
By proper selection of input addresses, both banks can be put in tri-state mode.
In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes.
In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated.
In this mode, the device will draw less than 25µA.
The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock.
(See available options table.
) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs.
The IDT2308 is characterized for both Industrial and Commercial operation.
NOTE: For new designs, refer to AN-233.
FUNCTIONAL BLOCK DIAGRAM (-3, -4) FBK REF 16 1 2 (-5) 2 PLL 3 2 CLKA1 CLKA2 14 CLKA3 15...

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