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GTL2008 Datasheet PDF

NXP
Part Number GTL2008
Manufacturer NXP
Title (GTL2008 / GTL2107) 12-Bit GTL to LVTTL Transistor
Description The GTL2008/GTL2107 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and G...
Features I Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver I EN1 and EN2 disable error output I All LVTTL and GTL outputs are put in a high-impedance state when EN1 and EN2 are LOW I 3.0 V to 3.6 V operation I LVTTL I/O not 5 V tolerant DataSheet 4 U .com www.DataSheet4U.com Philips Se...

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GTL2002 : The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.0 V without use of a direction pin. When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). Whe.

GTL2003 : The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 0.8 V and 5.0 V without use of a direction pin. Voltage translation below 0.8 V can be achieved when properly biased. For more information, refer to application note AN11127 (Ref. 1). When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the Sn and Dn ports. Assuming the higher voltage .

GTL2004 : The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from the GTL bus. LVTTL/TTL to GTL/GTL+ driver PIN CONFIGURATION A0 1 16 VCC LE0 2 A1 3 LE1 4 A2 5 LE2 6 A3 7 GND 8 15 DIR 14 B0 13 B1 12 B2 11 B3 10 GTLREF 9 LE3 SW00318 PIN DESCRIPTION PIN NUMBER 15 1, 3, 5, 7 11, 12, 13, 14 2, 4, 6, 9 10 8 16 SYMBOL DIR A0 – A3 B0 – B3 LE0 – LE3 GTLREF GND VCC NAME AND FUNCTION Direction control input Data inputs/outputs (A side, GTL) Data inputs/outputs (B side, TTL) Latch ena.

GTL2005 : The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. GND 7 SW00321 QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN CI/O PARAMETER Propagation delay An to Bn or Bn to An Input capacitance DIR I/O pin capacitance CONDITIONS Tamb = 25°C CL = 50 pF; VCC = 3.3 V VI = 0 V or VCC Outputs disabled; VI/O = 0 V or 3.0 V TYPICAL B to A A to B 2.1 1.9 3.0 7.8 4.1 4.3 3.0 4.5 UNIT ns pF pF ORDERING INFORMATION PACKAGES 14-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C ORDER CODE GTL2005 PW DH DWG NUMBER SOT402-1 PIN DESCRIPTION P.

GTL2006 : The GTL2006 is a 13-bit translator to interface between the 3.3 V LVTTL chip set I/O and the Xeon™ processor GTL–/GTL/GTL+ I/O. The GTL2006 is designed for platform health management in dual processor applications. SW01091 Figure 1. Pin configuration PIN DESCRIPTION PIN NUMBER 1 2–6, 8, 10–13, 15 7, 9, 16, 17–27 14 28 SYMBOL VREF nAn nBn GND VCC NAME AND FUNCTION GTL reference voltage Data inputs/outputs (LVTTL) Data inputs/outputs (GTL–/GTL/GTL+) Ground (0 V) Positive supply voltage QUICK REFERENCE DATA SYMBOL tPLH tPHL CI/O PARAMETER Propagation delay An to Bn or Bn to An I/O pin capacitance CONDITIONS Tamb = 25 °C CL = 50 pF; VCC = 3.3 V Outputs disabled; VI/O = 0 V or 3.0 V TYPICAL U.

GTL2007 : The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. The GTL2007 is derived from the GTL2006 with an enable function added that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. This enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. This unexpected power-down could be from a power supply overload, a CPU thermal trip, or some other event of which the monitoring agent is unaware. A typical implementation would be to connect eac.

GTL2009 : The GTL2009 is designed for the Nocona and Dempsey/Blackford dual Intel Xeon processor platforms to compare the Front-Side Bus (FSB) frequency settings and set the common FSB frequency at the lowest setting if both processor slots are occupied or the FSB setting of the occupied processor slot if only one processor is being used. A default FSB frequency of 100 MHz is initially set upon power-up when VDD is greater than 1.5 V. Magnitude comparisons and frequency multiplexing to compute the common FSB frequency occurs when the two 3-bit FSB GTL inputs from the chip sets are valid. The common FSB frequency GTL outputs switch from the default frequency to the computed frequency when the GTL refer.

GTL2010 : The GTL2010 is a high speed 10-bit voltage clamp. The low ON-state resistance of the clamp allows connections to be made with minimal propagation delay. The device is organized as one 10-bit voltage clamp. When S or D is low, the clamp is in the ON–state and a low resistance connection exists between the S and D ports. When S port and D port are high, the clamp is in the OFF-state and a very high impedance exists between the S and D ports. When port D is high, the voltage on the S port is clamped to the applied reference voltage on the GREF port. PIN CONFIGURATION GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S5 7 S6 8 S7 9 S8 10 S9 11 S10 12 24 23 22 21 20 19 18 17 16 15 14 13 GREF DREF D1 D2 D3 D4 D5 .

GTL2014 : The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface with a GTL−/GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or as a LVTTL to GTL interface. The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant. The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications. 2. Features s Operates as a 4-bit GTL−/GTL/GTL+ sampling receiver or as a LVTTL to GTL−/GTL/GTL+ driver s 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input s GTL input and .

GTL2020 : The GTL202x series are 32-bit bus switches with GTL termination and octal output enables. The GTL202x is intended to provide GTL bus termination in multi-processor environments. The enable pins allow the system control to disconnect the bus termination. When the bus switch is enabled, a 56, 75, 100 or 150 Ω series resistance is connected to the GTL Vbias. EN2 16 A16 17 A17 18 A18 19 A19 20 GND 21 VBIAS3A 22 EN3 23 A24 24 A25 25 A26 26 A27 27 GND 28 SW00473 QUICK REFERENCE DATA SYMBOL tPE/PD CON COFF PARAMETER Bus enable/disable Input capacitance switch on Input capacitance switch off CONDITIONS Tamb = 25°C; GND = 0V CL = 20 pF, RL = 500 Ω VIN = 0 V VIN = 0 V TYPICAL 2.5 3 6 UNIT nS pF pF .

GTL2021 : The GTL202x series are 32-bit bus switches with GTL termination and octal output enables. The GTL202x is intended to provide GTL bus termination in multi-processor environments. The enable pins allow the system control to disconnect the bus termination. When the bus switch is enabled, a 56, 75, 100 or 150 Ω series resistance is connected to the GTL Vbias. EN2 16 A16 17 A17 18 A18 19 A19 20 GND 21 VBIAS3A 22 EN3 23 A24 24 A25 25 A26 26 A27 27 GND 28 SW00473 QUICK REFERENCE DATA SYMBOL tPE/PD CON COFF PARAMETER Bus enable/disable Input capacitance switch on Input capacitance switch off CONDITIONS Tamb = 25°C; GND = 0V CL = 20 pF, RL = 500 Ω VIN = 0 V VIN = 0 V TYPICAL 2.5 3 6 UNIT nS pF pF .

GTL2022 : The GTL202x series are 32-bit bus switches with GTL termination and octal output enables. The GTL202x is intended to provide GTL bus termination in multi-processor environments. The enable pins allow the system control to disconnect the bus termination. When the bus switch is enabled, a 56, 75, 100 or 150 Ω series resistance is connected to the GTL Vbias. EN2 16 A16 17 A17 18 A18 19 A19 20 GND 21 VBIAS3A 22 EN3 23 A24 24 A25 25 A26 26 A27 27 GND 28 SW00473 QUICK REFERENCE DATA SYMBOL tPE/PD CON COFF PARAMETER Bus enable/disable Input capacitance switch on Input capacitance switch off CONDITIONS Tamb = 25°C; GND = 0V CL = 20 pF, RL = 500 Ω VIN = 0 V VIN = 0 V TYPICAL 2.5 3 6 UNIT nS pF pF .

GTL2023 : The GTL202x series are 32-bit bus switches with GTL termination and octal output enables. The GTL202x is intended to provide GTL bus termination in multi-processor environments. The enable pins allow the system control to disconnect the bus termination. When the bus switch is enabled, a 56, 75, 100 or 150 Ω series resistance is connected to the GTL Vbias. EN2 16 A16 17 A17 18 A18 19 A19 20 GND 21 VBIAS3A 22 EN3 23 A24 24 A25 25 A26 26 A27 27 GND 28 SW00473 QUICK REFERENCE DATA SYMBOL tPE/PD CON COFF PARAMETER Bus enable/disable Input capacitance switch on Input capacitance switch off CONDITIONS Tamb = 25°C; GND = 0V CL = 20 pF, RL = 500 Ω VIN = 0 V VIN = 0 V TYPICAL 2.5 3 6 UNIT nS pF pF .

GTL2034 : The GTL2034 is a 4-bit GTL−/GTL/GTL+ bus buffer. The GTL2034 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage open-drain output applications. 2. Features Operates as a 4-bit GTL−/GTL/GTL+ to GTL−/GTL/GTL+ bus buffer 3.0 V to 3.6 V operation GTL input and output 3.6 V tolerant Vref adjustable from 0.5 V to VCC / 2 Partial power-down permitted ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-CC101 s Latch-up protection exceeds 500 mA per JESD78 s Package offered: TSSOP14 s s s s s s 3. Quick reference data Table 1: Quick reference data Tamb = 25 °C Symbol tPLH tPHL Ci Parameter LOW-to-HIGH propa.




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