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IDT71P74604

Part Number	IDT71P74604
Manufacturer	IDT
Description	(IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4
Published	Nov 30, 2006
Detailed Description	www.DataSheet4U.com 18Mb Pipelined QDR™II SRAM Burst of 4 Features x x x x x x Description Advance Information IDT71P...
Datasheet	IDT71P74604 PDF File

Overview

www.
DataSheet4U.
com 18Mb Pipelined QDR™II SRAM Burst of 4 Features x x x x x x Description Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 x x x x x x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output 4-Word Burst on all SRAM accesses Multiplexed Address Bus One Read or One Write request per clock cycle DDR (Double Data Rate) Data Bus Four word burst data per two clock cycles on each port Four word transfers per clock cycle Depth expansion through Control Logic HSTL (1.
5V) inputs that can be scaled to receive signals from 1.
4V to 1.
9V.
Scalable output drivers Can drive HSTL, 1.
8V TTL or any voltage level from 1.
4V to 1.
9V.
Output Impedance adjustable from 35 ohms to 70 ohms 1.
8V Core Voltage (VDD) 165-ball, 1.
0mm pitch, 15mm x 17mm fBGA Package JTAG Interface The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports.
This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write.
Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance.
Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds.
Considering that QDRII allows clock speeds in excess of standard SRAM devices, the throughput can be increased well beyond four to one in most applications.
Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses.
All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds.
The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance.
The QDRII ...

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IDT71P74604 (IDT71P74x04) 18Mb Pipelined QDR II SRAM Burst of 4 - IDT

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