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W982508AH

Part Number	W982508AH
Manufacturer	Winbond
Description	8M X 4 BANKS X 8 BIT SDRAM
Published	Dec 9, 2006
Detailed Description	www.DataSheet4U.com W982508AH 8M × 4 BANKS × 8 BIT SDRAM GENERAL DESCRIPTION W982508AH is a high-speed synchronous dyna...
Datasheet	W982508AH PDF File

Overview

www.
DataSheet4U.
com W982508AH 8M × 4 BANKS × 8 BIT SDRAM GENERAL DESCRIPTION W982508AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 8M words × 4 banks × 8 bits.
Using pipelined architecture and 0.
175 µm process technology, W982508AH delivers a data bandwidth of up to 143M words per second (-7).
To fully comply with the personal computer industrial standard, W982508AH is sorted into three speed grades: -7, -75 and 8H.
The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification Accesses to the SDRAM are burst oriented.
Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the SDRAM internal counter in burst operation.
Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance.
W982508AH is ideal for main memory in high performance applications.
FEATURES • • • • • • • • • • • • • 3.
3V ±0.
3V Power Supply Up to 143 MHz Clock Frequency 8,388,608 Words × 4 Banks × 8 Bits Organization Auto Refresh and Self Refresh CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8, and Full Page Burst Read, Single Writes Mode Byte Data Controlled by DQM Power-down Mode Auto-precharge and Controlled Precharge 4K Refresh Cycles/64 mS Interface: LVTTL Packaged in TSOP II 54-pin, 400 mil - 0.
80 KEY PARAMETERS SYM.
DESCRIPTION MIN.
/MAX.
-7 (PC133, CL2) -75 (PC133, CL3) -8H (PC100) tCK tAC tRP tRCD ICC1 ICC4 ICC6 Clock Cycle Time Access Time from CLK Precharge to Active Command Active to Read/Write Command Operation Current (Single bank) Bu...

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