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ICS87931I

Part Number	ICS87931I
Manufacturer	ICS
Description	LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Published	Jan 2, 2007
Detailed Description	www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS87931I LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DEL...
Datasheet	ICS87931I PDF File

Overview

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DataSheet4U.
com Integrated Circuit Systems, Inc.
ICS87931I LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER FEATURES • Fully integrated PLL • 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications • Maximum output frequency: 150MHz • VCO range: 220MHz to 480MHz • External feedback for “zero delay” clock regeneration • Output skew, Same Frequency: 300ps (maximum) • Output skew, Different Frequency: 400ps (maximum) • Cycle-to-cycle jitter: 100ps (maximum) • 3.
3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC931 GENERAL DESCRIPTION The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”.
,&6 Selectable clock inputs, CLK1 and differential CLK0, nCLK0 support redundant clock applications.
The CLK_SEL input determines which reference clock is used.
The output divider values of Bank A, B and C are controlled by the DIV_SELA, DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed.
When LOW, the nMR input resets the internal dividers and forces the outputs to the high impedance state.
The effective fanout of the ICS87931I can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines.
PIN ASSIGNMENT DIV_SELC DIV_SELB DIV_SELA GND VDDO QA0 QA1 nc 32 31 30 29 28 27 26 25 nc VDDA POWER_DN CLK1 nMR CLK0 nCLK0 GND 1 2 3 4 5 6 7 8 24 23 GND QB0 QB1 VDDO EXTFB_SEL CLK_SEL PLL_SEL nc ICS87931I 32-Lead LQFP 7mm x 7mm x 1.
4mm...

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