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ZBNG4001

Zetex Semiconductors
Part Number ZBNG4001
Manufacturer Zetex Semiconductors
Description FET BIAS CONTROLLER
Published Jan 4, 2007
Detailed Description www.DataSheet4U.com FET BIAS CONTROLLER ISSUE 2 - JUNE 1998 DEVICE DESCRIPTION The ZNBG series of devices are designed ...
Datasheet PDF File ZBNG4001 PDF File

ZBNG4001
ZBNG4001

Overview
www.
DataSheet4U.
com FET BIAS CONTROLLER ISSUE 2 - JUNE 1998 DEVICE DESCRIPTION The ZNBG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc.
with a minimum of external components.
With the addition of two capacitors and resistors the devices provide drain voltage and current control for a number of external grounded source FETs, generating the regulated negative rail required for FET gate biasing whilst operating from a single supply.
This negative bias, at -3 volts, can also be used to supply other external circuits.
The ZNBG4000/1 and ZNBG6000/1 contain four and six bias stages respectively.
In setting drain current the ZNBG4000/1 two resistors allows individual FET pair control to different levels, the ZNBG6000/1 two resistors split control between two and four FETs.
This allows the operating current of input FETs to be adjusted to minimise noise, whilst the following FET stages can separately be adjusted for maximum gain.
The series also offers the choice of drain v ol t a ge t o b e s e t f or t he F E T s , the ZNBG4000/6000 gives 2.
2 volts drain whilst the ZNBG4001/6001 gives 2 volts.
ZNBG4000 ZNBG4001 ZNBG6000 ZNBG6001 These devices are unconditionally stable over the full working temperature with the FETs in place, subject to the inclusion of the recommended gate and drain capacitors.
These ensure RF stability and minimal injected noise.
It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections can be left open circuit without affecting operation of the remaining bias circuits.
In order to protect the external FETs the circuits have been designed to ensure that, under any conditions including power up/down transients, the gate drive from the bias circuits cannot exceed the range -3.
5V to 0.
7V.
Furthermore if the negative rail experiences a fault condition, such as overload or short circuit, the dr...


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