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MT5C6401

Part Number	MT5C6401
Manufacturer	Micron Technology
Description	64K x 1 SRAM
Published	Jan 5, 2007
Detailed Description	www.DataSheet4U.com OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM SRAM FEATURES • High speed: 9, 10, 12, 15, 20 and 25ns • H...
Datasheet	MT5C6401 PDF File

Overview

www.
DataSheet4U.
com OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM SRAM FEATURES • High speed: 9, 10, 12, 15, 20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with /C/E option • All inputs and outputs are TTL-compatible 64K x 1 SRAM PIN ASSIGNMENT (Top View) 22-Pin DIP (SA-2) A0 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 Vcc A15 A14 A13 A12 A11 A10 A9 A8 D CE OPTIONS • Timing 9ns access 10ns access 12ns access 15ns access 20ns access 25ns access • Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) • 2V data retention • Temperature Commercial Industrial Automotive Extended MARKING - 9 -10 -12 -15 -20 -25 A1 A2 A3 A4 A5 A6 A7 Q None DJ L WE Vss 24-Pin SOJ (SD-1) A0 A1 A2 A3 A4 A5 NC A6 A7 Q WE Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vcc A15 A14 A13 A12 NC A11 A10 A9 A8 D CE (0°C to +70°C) (-40°C to +85°C) (-40°C to +125°C) (-55°C to +125°C) None IT AT XT • Part Number Example: MT5C6401DJ-10 L NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available.
Please contact the factory for availability of specific part number combinations.
GENERAL DESCRIPTION The MT5C6401 is organized as a 65,556 x 1 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS process.
Micron SRAMs are fabricated using doublelayer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Micron offers chip enable (/C/E) with all organizations.
This enhancement can place the outputs in High-Z for additional flexibility in system design.
The x1 configuration features separate data input and output.
MT5C6401 REV.
12/93 Writing to these devices is accomplished when write enable (?W/E) and /C/E inputs are both LOW.
Reading is accomplished when ?W/E remains HIGH and /C/E goes to LOW.
The device offers a reduced power standby mode when disabled.
This allows system designe...

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