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ADSP-21366

Analog Devices
Part Number ADSP-21366
Manufacturer Analog Devices
Description SHARC Processor
Published Jan 17, 2007
Detailed Description SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY High performance 32-bit/40-bit floating...
Datasheet PDF File ADSP-21366 PDF File

ADSP-21366
ADSP-21366


Overview
SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bits of on-chip SRAM Code compatible with all other members of the SHARC family The ADSP-2136x processors are available with up to 333 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more.
For complete ordering information, see Ordering Guide on Page 56.
DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios Available in 136-ball CSP_BGA and 144-lead LQFP_EP packages SIMD Core Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy FLAGx/IRQx/ TMREXP JTAG Block 0 RAM/ROM Internal Memory Block 1 RAM/ROM Block 2 RAM Block 3 RAM DMD 64-BIT PMD 64-BIT S Core Bus Cross Bar DMD 64-BIT PMD 64-BIT B0D 64-BIT PERIPHERAL BUS 32-BIT B1D 64-BIT B2D 64-BIT B3D 64-BIT Internal Memory I/F IOD 32-BIT PERIPHERAL BUS IOD BUS MTM/ DTCP CORE TIMER ASRC S/PDIF PCG FLAGS 2-0 3-0 Tx/Rx A-B SPI B PDAP/ SPORT IDP7-0 5-0 SPI Core Flags PWM 3-0 PP DAI Peripherals DAI Routing/Pins PP Pin MUX Peripherals Figure 1.
Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev.
J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliabl...



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