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HY5V22FP

Hynix Semiconductor
Part Number HY5V22FP
Manufacturer Hynix Semiconductor
Description 4 Banks x 1M x 32Bit Synchronous DRAM
Published Jan 21, 2007
Detailed Description www.DataSheet4U.com HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision ...
Datasheet PDF File HY5V22FP PDF File

HY5V22FP
HY5V22FP

Overview
www.
DataSheet4U.
com HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision No.
0.
1 History Defined Preliminary Specification 1) 2) 3) 4) 5) 6) Modified FBGA Ball Configuration Typo.
Changed Functional Block Diagram from A10 to A11.
Changed VDD min from 3.
0V to 3.
135V.
Changed Cap.
Value from C11, 3, 5 to 4pf & C12, 3.
8 to 4pf.
Insert tAC2 Value.
Insdrt tRAS & CLK Value.
Remark 0.
2 0.
3 0.
4 0.
5 0.
6 0.
7 0.
8 0.
9 Defined IDD Spec.
Delited Preliminary.
Changed IDD Spec.
133MHz Speed Added Changed FBGA Package Size from 11x13 to 8x13.
1) Changed VDD min from 3.
135V to 3.
0V.
2) Changed VIL min from VSSQ-0.
3V to -0.
3V.
Modified of size erra.
(Page15) (Equation : 13.
00 ± 10 -> 13.
00 ± 0.
10) This document is a general product description and is subject to change without notice.
Hynix Semiconductor Inc.
does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
9 / July 2004 HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM DESCRIPTION The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth.
HY57V283220(L)T(P) / HY5V22(L)F(P) is organized as 4banks of 1,048,576x32.
HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock.
All inputs and outputs are synchronized with the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth.
All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
A burst of read or write cycles in progress can be terminated by a burst terminate command or ...


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