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NT5SV16M16AT

Nanya
Part Number NT5SV16M16AT
Manufacturer Nanya
Description (NT5SVxxMxxAT) Synchronous DRAM
Published Jan 24, 2007
Detailed Description www.DataSheet4U.com NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Features • High Performance: ...
Datasheet PDF File NT5SV16M16AT PDF File

NT5SV16M16AT
NT5SV16M16AT

Overview
www.
DataSheet4U.
com NT5SV64M4AT(L) NT5SV32M8AT(L) NT5SV16M16AT(L) 256Mb Synchronous DRAM Features • High Performance: -7K 3 CL=2 fCK tCK tAC tAC Clock Frequency Clock Cycle Clock Access Time 1 133 7.
5 — 5.
4 -75B, CL=3 133 7.
5 — 5.
4 -8B, CL=2 100 10 — 6 Units MHz ns ns ns Clock Access Time 2 1.
Terminated load.
See AC Characteristics on page 37.
2.
Unterminated load.
See AC Characteristics on page 37.
3.
tRP = tRCD = 2 CKs • • • • • • • • • • • • Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 8192 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.
3V ± 0.
3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II • • • • • • Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BA0/BA1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8 Programmable Wrap: Sequential or Interleave • -7K parts for PC133 2-2-2 operation -75B parts for PC133 3-3-3 operation -8B parts for PC100 2-2-2 operation Description The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively.
These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock.
The chip is fabricated with NTC’s advanced 256Mbit single transistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically.
All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock.
RAS, CAS, WE, and CS are pul...


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