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ATT3042

Lucent
Part Number ATT3042
Manufacturer Lucent
Description (ATT3000 Series) Field-Programmable Gate Arrays
Published Jan 25, 2007
Detailed Description www.DataSheet4U.com Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Features s Description The...
Datasheet PDF File ATT3042 PDF File

ATT3042
ATT3042

Overview
www.
DataSheet4U.
com Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Features s Description The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of highdensity, digital integrated circuits.
Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection.
The general structure of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development System provides automatic place and route of netlists.
Logic and timing simulation are available as design verification alternatives.
The design editor is used for interactive design optimization and to compile the data pattern that represents the configuration program.
The FPGA’s user-logic functions and interconnections are determined by the configuration program data stored in internal static memory cells.
The program can be loaded in any of several modes to accommodate various system requirements.
The program data resides externally in an EEPROM, EPROM, or ROM on the application circuit board, or on a floppy disk or hard disk.
On-chip initialization logic provides for optional automatic loading of program data at powerup.
A serial configuration PROM can provide a very simple serial configuration program storage.
* Xilinx, XC3000, and XC3100 are registered trademarks of Xilinx, Inc.
High performance: — Up to 270 MHz toggle rates — 4-input LUT delays <2.
7 ns User-programmable gate arrays — Unlimited reprogrammability — Easy design iteration through in-system logic changes Flexible array architecture: — Compatible arrays ranging from 1500 to 6000 gate logic complexity — Extensive register, combinatorial, and I/O capabilities — Low-skew clock nets — High fan-out signal distribution — Internal 3-state bus capabilities — TTL or CMOS input thresholds — On-chip oscillator amplifier Standard pr...


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