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FLX257XV

Part Number	FLX257XV
Manufacturer	Eudyna Devices
Description	GaAs FET & HEMT Chips
Published	Feb 3, 2007
Detailed Description	www.DataSheet4U.com FLX257XV GaAs FET & HEMT Chips FEATURES • • • • High Output Power: P1dB = 33.5dBm(Typ.) High Gain:...
Datasheet	FLX257XV PDF File

Overview

www.
DataSheet4U.
com FLX257XV GaAs FET & HEMT Chips FEATURES • • • • High Output Power: P1dB = 33.
5dBm(Typ.
) High Gain: G1dB = 7.
5dB(Typ.
) High PAE: ηadd = 31%(Typ.
) Proven Reliability 95 40 (Unit: µm) DESCRIPTION The FLX257XV chip is a power GaAs FET that is designed for general purpose applications in the X-Band frequency range as it provides superior power, gain, and efficiency.
Eudyna’s stringent Quality Assurance Program assures the highest reliability and consistent performance.
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C) Item Drain-Source Voltage Gate-Source Voltage Total Power Dissipation Storage Temperature Channel Temperature Symbol VDS VGS Ptot Tstg Tch Condition Rating 15 -5 Tc = 25°C 15.
0 -65 to +175 175 Unit V V W °C °C Gate Gate Gate Eudyna recommends the following conditions for the reliable operation of GaAs FETs: 1.
The drain-source operating voltage (VDS) should not exceed 10 volts.
2.
The forward and reverse gate currents should not exceed 17.
8 and -1.
2 mA respectively with gate resistance of 200Ω.
3.
The operating channel temperature (Tch) should not exceed 145°C.
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C) Item Saturated Drain Current Transconductance Pinch-off Voltage Gate Source Breakdown Voltage Output Power at 1dB Gain Compression Point Power Gain at 1dB Gain Compression Point Power-added Efficiency Thermal Resistance Symbol IDSS gm Vp VGSO P1dB G1dB ηadd Rth Channel to Case VDS = 10V IDS ≈ 0.
6IDSS f = 10GHz Test Conditions VDS = 5V, VGS = 0V VDS = 5V, IDS = 600mA VDS = 5V, IDS = 50mA IGS = -50µA Min.
-1.
0 -5 32.
5 6.
5 Limit Typ.
Max.
1000 600 -2.
0 33.
5 7.
5 31 8 1500 -3.
5 10 Unit mA mS V V dBm dB % °C/W Note: RF parameter sample size 10pcs.
criteria (accept/reject)=(2/3) The chip must be enclosed in a hermetically sealed environment for optimum performance and reliability.
Edition 1.
4 October 2004 1 56 40 Drain Drain Drain Drain FLX257XV GaAs FET & HEMT Chips POWER DERATING CURVE DRAIN CURRENT vs.
DRAI...

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FLX257XV GaAs FET & HEMT Chips - Eudyna Devices

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