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MC54HC574A

Motorola
Part Number MC54HC574A
Manufacturer Motorola
Description OCTAL 3-STARE NONINVERTING D FLIP-FLOP
Published Feb 11, 2007
Detailed Description www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Noninverting D Flip-Flop High–Performance Sil...
Datasheet PDF File MC54HC574A PDF File

MC54HC574A
MC54HC574A

Overview
www.
DataSheet4U.
com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Noninverting D Flip-Flop High–Performance Silicon–Gate CMOS The MC54/74HC574A is identical in pinout to the LS574.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising edge of the Clock.
The Output Enable input does not affect the states of the flip–flops, but when Output Enable is high, all device outputs are forced to the high–impedance state.
Thus, data may be stored even when the outputs are not enabled.
The HC574A is identical in function to the HCT374A but has the flip–flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.
The HC574A is the noninverting version of the HC564.
• • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.
0 to 6.
0 V Low Input Current: 1.
0 µA In Compliance with the Requirements Defined by JEDEC Standard No.
7A • Chip Complexity: 266 FETs or 66.
5 Equivalent Gates MC54/74HC574A 20 1 J SUFFIX CERAMIC PACKAGE CASE 732–03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW Ceramic Plastic SOIC PIN ASSIGNMENT LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D7 GND 9 10 12 11 Q7 CLOCK NON– INVERTING OUTPUTS OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ Design Criteria Value 66.
5 1.
5 5.
0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product ...


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