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K7Q161882A

Samsung semiconductor
Part Number K7Q161882A
Manufacturer Samsung semiconductor
Description (K7Q161882A / K7Q161882A) 512Kx36 & 1Mx18 QDR b2 SRAM
Published Mar 23, 2007
Detailed Description www.DataSheet4U.com K7Q163682A K7Q161882A Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM 512Kx36 & 1Mx18 QDRTM b2 SR...
Datasheet PDF File K7Q161882A PDF File

K7Q161882A
K7Q161882A

Overview
www.
DataSheet4U.
com K7Q163682A K7Q161882A Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM 512Kx36 & 1Mx18 QDRTM b2 SRAM Revision History Rev.
No.
0.
0 0.
1 History 1.
Initial document.
1.
Icc, Isb addition 2.
1.
8V Vddq addition 3.
Speed bin change 1.
Changed Pin configuration at x36 organization.
- 9F ; from Q14 to D14 .
- 10F ; from D14 to Q14 .
2.
Reserved pin for high density name change from NC to Vss/SA 1.
Final SPEC release 2.
Modify thermal resistance Draft Date May, 22 2001 Remark Advance Sep,03 2001 Advance 0.
2 Nov.
20.
2001 Preliminary 1.
0 July, 03.
2002 Final The attached data sheets are prepared and approved by SAMSUNG Electronics.
SAMSUNG Electronics CO.
, LTD.
reserve the right to change the specifications.
SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device.
If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1- July 2002 Rev 1.
0 K7Q163682A K7Q161882A 512Kx36-bit, 1Mx18-bit QDRTM SRAM FEATURES • 1.
8V+0.
1V/-0.
1V Power Supply.
• I/O Supply Voltage 1.
5V+0.
1V/-0.
1V for 1.
5V I/O, 1.
8V+0.
1V/-0.
1V for 1.
8V I/O.
• Separate independent read and write data ports with concurrent read and write operation • HSTL I/O • Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two Input clocks(K and K) for accurate DDR timing at clock rising edges only.
• Two Input clocks for output data(C and C) to minimize clockskew and flight-time mismatches.
• Single address bus.
• Byte writable function.
• Sepatate read/write control pin(R and W) • Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.
1 compatible test access port.
• 165FBGA(11x15 ball ...


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