DatasheetsPDF.com

MB82DBS04163C

Fujitsu Media Devices
Part Number MB82DBS04163C
Manufacturer Fujitsu Media Devices
Description MEMORY Mobile FCRAMTM CMOS 64 M Bit
Published Apr 9, 2007
Detailed Description www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-11432-1E MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 ...
Datasheet PDF File MB82DBS04163C PDF File

MB82DBS04163C
MB82DBS04163C

Overview
www.
DataSheet4U.
com FUJITSU SEMICONDUCTOR DATA SHEET DS05-11432-1E MEMORY Mobile FCRAMTM CMOS 64 M Bit (4 M word×16 bit) MB82DBS04163C-70L ■ DESCRIPTION Mobile Phone Application Specific Memory The FUJITSU MB82DBS04163C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 67,108,864 storages accessible in a 16-bit format.
MB82DBS04163C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in comparison to regular SRAM.
The MB82DBS04163C adopts asynchronous page mode and synchronous burst mode for fast memory access as user configurable options.
This MB82DBS04163C is suited for mobile applications such as Cellular Handset and PDA.
* : FCRAM is a trademark of FUJITSU LIMITED, Japan ■ PRODUCT LINEUP Parameter Access Time (Max) (tCE, tAA) Access Time from CLK (Max) (tAC) Active Current (Max) (IDDA1) Standby Current (Max) (IDDS1) Power Down Current (Max) (IDDPS) MB82DBS04163C-70L 70 ns 10 ns 35 mA 90 µA 10 µA RL = 6, 5 TA ≤ + 40 °C ■ FEATURES • • • • • • • • Asynchronous SRAM Interface Fast Access Time : tCE = 70 ns Max 8 words Page Access Capability : tPAA = 20 ns Max Burst Read/Write Access Capability : tAC = 10 ns Max Low Voltage Operating Condition : VDD = 1.
7 V to 1.
95 V Wide Operating Temperature : TA = -30 °C to +85 °C Byte Control by LB and UB Low-Power Consumption : IDDA1 = 35 mA Max IDDS1 = 90 µA Max (TA ≤ + 40°C ) • Various Power Down mode : Sleep 8 M-bit Partial 16 M-bit Partial • Shipping Form : Wafer/Chip MB82DBS04163C-70L ■ PIN DESCRIPTION Pin Name A21 to A0 CE1 CE2 WE OE LB UB CLK ADV WAIT DQ8 to DQ1 DQ16 to DQ9 VDD VSS Address Input Chip Enable 1 (Low Active) Chip Enable 2(High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Clock Input Address Valid Input (Low Active) Wait Output Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Voltage Ground Des...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)