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PDSP16488A

Zarlink Semiconductor
Part Number PDSP16488A
Manufacturer Zarlink Semiconductor
Description Single Chip 2D Convolver
Published Apr 10, 2007
Detailed Description www.DataSheet4U.com PDSP16488A Single Chip 2D Convolver with Integral Line Delays Advance Information DS3713 ISSUE 6.4...
Datasheet PDF File PDSP16488A PDF File

PDSP16488A
PDSP16488A

Overview
www.
DataSheet4U.
com PDSP16488A Single Chip 2D Convolver with Integral Line Delays Advance Information DS3713 ISSUE 6.
4 December 1997 The PDSP16488A is a fully integrated, application specific, image processing device.
It performs a two dimensional convolution between the pixels within a video window and a set of stored coefficients.
An internal multiplier accumulator array can be multi-cycled at double or quadruple the pixel clock rate.
This then gives the window size options listed in Table 1.
An internal 32kbit RAM can be configured to provide either four or eight line delays.
The length of each delay can be programmed to the users requirement, up to a maximum of 1024 pixels per line.
The line delays are arranged in two groups,which may be internally connected in series or may be configured to accept separate pixel inputs.
This allows interlaced video or frame to frame operations to be supported.
The 8-bit coefficients are also stored internally and can be downloaded from a host computer or from an EPROM.
No additional logic is required to support the EPROM and a single device can support up to 16 convolvers.
The PDSP16488A contains an expansion adder and delay network which allows several devices to be cascaded.
Convolvers with larger windows can then be fabricated as shown in Table 2.
Intermediate 32-bit precision is provided to avoid any danger of overflow, but the final result will not normally occupy all bits.
The PDSP16488A thus provides a gain control block in the output path, which allows the user to align the result to the most significant end of the 32-bit word.
COMPOSITE DATA PIXEL CLOCK GEN SYNC ODD FIELD POWER EPROM ON ADDR DATA RESET CLK HRES BYPASS RES DELOP SYNC EXTRACT DELAYED SYNC PDSP16488A ADC OPTIONAL FIELD DELAY L7:0 D15:0 OUTPUT DATA IP7:0 Fig.
1 Typical stand-alone real time system Pixel Window size size Width Depth 8 8 8 16 16 4 8 8 4 8 4 4 8 4 4 Maximum pixel rate (MHz) 20 20 10 20 10 Line delays 431024 431024 83512 43512 43...


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