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MC74VHC1GT04

ETL
Part Number MC74VHC1GT04
Manufacturer ETL
Description Inverting Buffer / CMOS Logic Level Shifter
Published Apr 13, 2007
Detailed Description Inverting Buffer / CMOS Logic Level Shifter with LSTTL–Compatible Inputs MC74VHC1GT04 The MC74VHC1GT04 is a single gat...
Datasheet PDF File MC74VHC1GT04 PDF File

MC74VHC1GT04
MC74VHC1GT04


Overview
Inverting Buffer / CMOS Logic Level Shifter with LSTTL–Compatible Inputs MC74VHC1GT04 The MC74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing.
The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.
0 V CMOS logic to 5.
0V CMOS Logic or from 1.
8 V CMOS logic to 3.
0 V CMOS Logic while operating at the high–voltage power supply.
The MC74VHC1GT04 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.
This allows the MC74VHC1GT04 to be used to interface 5 V circuits to 3 V circuits.
The output structures also provide protection when V CC = 0 V.
These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch, battery backup, hot insertion, etc.
• High Speed: t PD = 3.
8 ns (Typ) at V CC = 5 V • Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C • TTL–Compatible Inputs: V IL = 0.
8 V; V IH = 2.
0 V • CMOS–Compatible Outputs: V OH > 0.
8 V CC ; V OL < 0.
1 V CC @Load • Power Down Protection Provided on Inputs and Outputs • Balanced Propagation Delays • Pin and Function Compatible with Other Standard Logic Families • Chip Complexity: FETs = 105; Equivalent Gates = 26 PIN ASSIGNMENT MARKING DIAGRAMS 5 4 www.
DataSheet4U.
com 1 2 3 VKd SC–70/SC–88A/SOT–353 DF SUFFIX CASE 419A Pin 1 d = Date Code 5 4 Figure 1.
Pinout (Top View) 1 2 3 VKd Figure 2.
Logic Symbol Pin 1 d = Date Code SOT–23/TSOP–5/SC–59 DT SUFFIX CASE 483 PIN ASSIGNMENT 1 2 3 4 5 NC IN A GND OUT Y ...


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