DatasheetsPDF.com

VP551E

Zarlink Semiconductor
Part Number VP551E
Manufacturer Zarlink Semiconductor
Description (VP531E / VP551E) NTSC/PAL Digital Video Encoder
Published Apr 17, 2007
Detailed Description Obsolescence Notice This product is obsolete. This information is available for your convenience only. www.DataSheet4U....
Datasheet PDF File VP551E PDF File

VP551E
VP551E

Overview
Obsolescence Notice This product is obsolete.
This information is available for your convenience only.
www.
DataSheet4U.
com For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.
zarlink.
com/obsolete_products/ VP531E/VP551E NTSC/PAL Digital Video Encoder Advance Information Supersedes DS4573 1.
4 May 1997 edition DS4573 - 2.
3 October1998 The VP531/VP551 converts digital Y, Cr, Cb, data into analog NTSC/PAL composite video and S-video signals The outputs are capable of driving doubly terminated 75 ohm loads with standard video levels.
The device accepts data inputs complying with CCIR Recommendation 601 and 656.
The data is time multiplexed on an 8 bit bus at 27MHz and is formatted as Cb, Y, Cr, Y (i.
e.
4:2:2).
The video blanking and sync information from REC 656 is included in the data stream when the VP531 is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate is half this frequency, i.
e.
13.
5MHz.
All necessary synchronisation signals are generated internally when the device is operating in master mode.
In slave mode the device will lock to the TRS codes or the HS and VS inputs.
The rise and fall times of sync, burst envelope and video blanking are internally controlled to be within composite video specifications.
Two 9 bit digital to analog converters (DACs) are used to convert the digital luminance and chrominance data into analog signals.
An inverted composite video signal is generated by summing the complementary current outputs of each DAC.
An internally generated reference voltage provides the biasing for the DACs.
PIN 64 PIN 1 GP64 Fig.
1 Pin connections (top view) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FUNCTION VDD GND D0 (VS I/O) D1 (HS I/O) D2 (FC0 O/P) D3 (FC1 O/P) D4 (FC2 O/P) D5 D6 (SCSYNC I/P) D7 (PALID I/P) GND VDD GND GND PXCK VDD CLAMP COMPSYNC GND VDD TDO TDI TMS TCK GND SA1 SA2 SCL VDD SDA GND VDD PIN 33 34 ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)