DatasheetsPDF.com

SY100S839V

Part Number	SY100S839V
Manufacturer	Micrel Semiconductor
Description	CLOCK GENERATION CHIP
Published	Apr 30, 2007
Detailed Description	Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS ÷2/4, ÷4/5/6 CLOCK GENERATION CHIP Precision Edge® PrecisionSYE1d00gSe8®3...
Datasheet	SY100S839V PDF File

Overview

Micrel, Inc.
NOT RECOMMENDED FOR NEW DESIGNS ÷2/4, ÷4/5/6 CLOCK GENERATION CHIP Precision Edge® PrecisionSYE1d00gSe8®39V SY100S839V FEATURES s 3.
3V and 5V power supply option s 50ps output-to-output skew s 50% duty cycle outputs s Synchronous enable/disable s Master Reset for synchronization s Internal 75KΩ input pull-down resistors s Available in 20-pin SOIC package Precision Edge® DESCRIPTION The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.
The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal.
In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device.
If a singleended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.
01µF capacitor.
The VBB output is designed to act as the switching reference for the input of the S839V under single-ended input conditions.
As a result, this pin can only source/sink up to 0.
5mA of current.
The common enable (/EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.
This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control.
An internal runt pulse could lead to losing synchronization between the internal divider stages.
The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input must be asserted to ensure synchronization.
For systems which only use one S839V, the MR pin need not b...

Similar Datasheet

SY100S834 Clock Generation Chip - Micrel Semiconductor
SY100S834L Clock Generation Chip - Micrel Semiconductor
SY100S838 CLOCK GENERATION CHIP - Micrel Semiconductor
SY100S838L CLOCK GENERATION CHIP - Micrel Semiconductor
SY100S839V CLOCK GENERATION CHIP - Micrel Semiconductor

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)