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HI7188

Intersil Corporation
Part Number HI7188
Manufacturer Intersil Corporation
Description Sigma-Delta A/D Sub-System
Published May 16, 2007
Detailed Description HI7188 August 1997 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System Description The HI7188 is an easy-to-u...
Datasheet PDF File HI7188 PDF File

HI7188
HI7188


Overview
HI7188 August 1997 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System Description The HI7188 is an easy-to-use 8-Channel sigma-delta programmable A/D subsystem ideal for low frequency physical and electrical measurements in scientific, medical, and industrial applications.
The subsystem has complete on-chip capabilities to support moving the intelligence from the system controller and towards the sensors.
This gives the designer faster and more flexible configurability without the traditional drawbacks of low throughput per channel, higher power or cost per channel.
Extreme design complexity and excessive software overhead is eliminated.
The HI7188 contains a fully differential 8 channel multiplexer, Programmable Gain Instrumentation Amplifier (PGIA), 4th order sigma-delta ADC, integrating filter, line noise rejection filters, calibration and data RAMs, clock oscillator, and a microsequencer.
Communication with the HI7188 is performed via the serial I/O port, and is compatible with most synchronous transfer formats, including both the Motorola/Intersil 6805/11 series SPI, QSPI and Intel 8051 series SSR protocols.
The powerful on-board microsequencer provides automatic conversions on the multiplexed input channels (up to 8) by controlling all channel switching, filtering and calibration.
The microsequencer supports on-the-fly multiplexer reconfiguration, forty to fifty times faster throughput than the competition and zero step response delay during internal or external multiplexer channel changes.
A simple set of commands gives the user control over calibration, PGIA gain, and bipolar/unipolar modes on a per channel basis.
Number of channels to convert, data coding, line noise rejection, etc.
is programmed at the chip level.
The calibration RAMs allow the user to read and write system calibration data while the data RAMs provide a read support of the conversion results for each channel.
This design is effectively eight 16-bit (for 96dB noise-free dynamic range) Sig...


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