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MT4C1004J883C

Austin Semiconductor
Part Number MT4C1004J883C
Manufacturer Austin Semiconductor
Description 4 MEG x 1 DRAM FAST PAGE MODE
Published Jun 7, 2007
Detailed Description AUSTIN SEMICONDUCTOR, INC. MT4C1004J MT5C1005 883C 4 MEG 256K x x1 4 DRAM SRAM DRAM AVAILABLE AS MILITARY SPECIFICATON...
Datasheet PDF File MT4C1004J883C PDF File

MT4C1004J883C
MT4C1004J883C


Overview
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J MT5C1005 883C 4 MEG 256K x x1 4 DRAM SRAM DRAM AVAILABLE AS MILITARY SPECIFICATONS • SMD 5962-90622 • MIL-STD-883 4 MEG x 1 DRAM FAST PAGE MODE PIN ASSIGNMENT (Top View) 18-Pin DIP D WE RAS *A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 Vss Q CAS A9 A8 A7 A6 A5 A4 20-Pin ZIP A9 Q D RAS NC A0 A2 Vcc A5 A7 1 3 5 7 9 11 13 15 17 19 FEATURES • Industry standard x1 pinout, timing, functions and packages • High-performance, CMOS silicon-gate process • Single +5V ± 10% power supply • Low-power, 2.
5mW standby; 300mW active, typical • All inputs, outputs and clocks are fully TTL and CMOS compatible • 1,024-cycle refresh distributed across 16ms • Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR), and HIDDEN • FAST PAGE MODE access cycle www.
DataSheet4U.
com • CBR with ?W/E a HIGH (JEDEC test mode capable via WCBR) 2 4 6 8 10 12 14 16 18 20 CAS Vss WE A10* NC A1 A3 A4 A6 A8 OPTIONS • Timing 70ns access 80ns access 100ns access 120ns access • Packages Ceramic DIP (300 mil) Ceramic DIP (400 mil) Ceramic LCC Ceramic SOJ Ceramic ZIP Ceramic Gull Wing MARKING - 7 - 8 -10 -12 20-Pin SOJ 20-Pin LCC 20-Pin Gull Wing D WE RAS NC *A10 1 2 3 4 5 26 25 24 23 22 Vss Q CAS NC A9 CN C ECN ECJ CZ ECG No.
101 No.
102 No.
202 No.
504 No.
400 No.
600 A0 A1 A2 A3 Vcc 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 *Address not used for /R/A/S-ONLY REFRESH GENERAL DESCRIPTION The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configuration.
During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time.
/R/A/S is used to latch the first 11 bits and /C/A/S the latter 11 bits.
A READ or WRITE cycle is selected with the ?W/E input.
A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode.
During a WRITE cycle, data-in (D) is latched by the MT4C1004J 883C REV.
11/97 DS000021 falli...


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