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W3E32M72S-XSBX

White Electronic
Part Number W3E32M72S-XSBX
Manufacturer White Electronic
Description 32Mx72 DDR SDRAM
Published Jun 8, 2007
Detailed Description White Electronic Designs 32Mx72 DDR SDRAM FEATURES „ „ „ „ „ „ „ „ „ Data rate = 200, 250, 266, 333Mbs Package: • 208 Pl...
Datasheet PDF File W3E32M72S-XSBX PDF File

W3E32M72S-XSBX
W3E32M72S-XSBX

Overview
White Electronic Designs 32Mx72 DDR SDRAM FEATURES „ „ „ „ „ „ „ „ „ Data rate = 200, 250, 266, 333Mbs Package: • 208 Plastic Ball Grid Array (PBGA), 16 x 22mm 2.
5V ±0.
2V core power supply 2.
5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.
e.
, source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 32M x 72 Weight: W3E32M72S-XSBX - 2.
5 grams typical W3E32M72S-XSBX BENEFITS „ „ „ „ „ „ „ 73% Space Savings vs.
TSOP • 44% Space Savings vs FPBGA Reduced part count 37% I/O reduction vs TSOP • 31% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match Upgradeable to 64M x 72 density (contact factory for information) „ „ „ „ „ „ „ „ „ „ GENERAL DESCRIPTION The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits.
Each chip is internally configured as a quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation.
The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bi...


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